• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.15 no.2
• /
• pp.23-29
• /
• 2015

The baby-step giant-step algorithm seeks b in a discrete logarithm problem when a,c,p of $a^b{\equiv}c$(mod p) are already given. It does so by dividing p by m block of $m={\lceil}{\sqrt{p}}{\rceil}$ length and letting one giant walk straight toward $a^0$ with constant m strides in search for b. In this paper, I basically reduce $m={\lceil}{\sqrt{p}}{\rceil}$ to p/l, $a^l$ > p and replace a giant with an adult who is designed to walk straight with constant l strides. I also extend the algorithm to allow $2^k$ adults to walk simultaneously. As a consequence, the proposed algorithm quarters the execution time of the basic adult-walk method when applied to $2^k$, (k=2) in the range of $1{\leq}b{\leq}p-1$. In conclusion, the proposed algorithm greatly shorten the step number of baby-step giant-step.

• Proceedings of the Korean Institute Of Construction Engineering and Management
• /
• autumn
• /
• pp.163-168
• /
• 2001

In the domestic construction field, there are a lot of problems related to construction information exchange and sharing owing to the absence of construction drawing information exchange standard. To solve the problems effectively, it is necessary to apply STEP standard that is international standard and standard technology for achieving the establishment of Construction CALS. This study focus on suggesting a methodology to solve problems which occur to the current construction drawing information exchanging and sharing practice. The domestic and foreign standardization projects related to the construction drawing information have been investigated and analyzed. In result, a methodology of applying the STEP standard has been suggested. In addition, a verification and certification methodology for applying the CALS/EC construction drawing information exchange standard(STEP) have been suggested.

• Journal of Korean Society of Water and Wastewater
• /
• v.25 no.5
• /
• pp.691-697
• /
• 2011

In this study, by using the Water footprint technique, the water consumption by washing machines, which holds higher ranks in using water than any other electric appliances, was analyzed during their life cycle. The life cycle is defined as raw materials production step, manufacturing step, and using step. In raw materials production step, Input materials were researched by using LCI DB(Life Cycle Inventory Database) and the water consumption was calculated with consideration of approximately 65% Input materials which were based weight. In manufacturing step, the water consumption was calculated by the amount of energy used in assembly factories and components subcontractors and emission factor of energy. In using step, referring to guidelines on carbon footprint labeling, the life cycle is applied as 5 years for a washing machine and 218 cycles for annual bounds of usage. The water and power consumption for operating was calculated by referring to posted materials on the manufacture's websites. The water consumption by nation unit was calculated with the result of water consumption by a unit of washing machine. As a result, it shows that water consumption per life cycle s 110,105 kg/unit. The water consumption of each step is 90,495 kg/unit for using, 18,603 kg for raw materials production and 1,006 kg/unit for manufacturing, which apparently shows that the using step consume the most water resource. The water consumption by nation unit is 371,269,584tons in total based on 2006, 83,385,649 tons in both steps of raw material production and manufacturing, and 287,883,935 tons in using step.

• The Transactions of the Korean Institute of Electrical Engineers P
• /
• v.63 no.4
• /
• pp.361-367
• /
• 2014

This paper is related to a new solar power conditioner for a built-in step-up chopper function. In the first step-up chopper proposed solar PV power conditioner for mutually connected in series with the input voltage of the bypass diodes are respectively connected to the positive terminal should install the mutual boosting chopper diode connected in series with the boost chopper switching element between the two power supply and at the same time the first and the second was connected to a second diode and a resonance inductor and a snubber capacitor in series with each other. And the common connection point between the bypass diode and the step-up chopper and the step-up chopper diode common connection point of the switching elements of the input voltage was set to the boost inductor for storing energy. In addition, between the step-up chopper and the step-up chopper diode and a switching element of a joint connection point of the first auxiliary diode and the second common connection point of the auxiliary diode was provided, the resonance capacitor. Between the step-up chopper and the step-up chopper diode and a switching element of a joint connection point and the common connection point of the resonance inductor snubber capacitor and connecting the third secondary diode, between two power supply lines is characterized by configuring the DC link capacitor bus lines in parallel. Therefore, it is possible to suppress the switching loss through, DC link bus lines, as well as there could seek miniaturization and weight reduction of the power conditioner itself by using a common capacitor of the non-polar non-polar electrolytic capacitor having a capacitor, the service life of the circuit can be extended and it is possible to greatly reduce the loss can be greatly improve the reliability of the product and the operation of the product itself.

• The Journal of the Acoustical Society of Korea
• /
• v.37 no.3
• /
• pp.156-162
• /
• 2018

The LMF (Least Mean Fourth) algorithm is well known for its fast convergence and low steady-state error especially in non-Gaussian noise environments. Recently, there has been increasing interest in the LMS (Least Mean Square) algorithms with self-adjusted step size. It is because the self-adjusted step-size LMS algorithms have shown to outperform the conventional fixed step-size LMS in the various situations. In this paper, a self-adjusted step-size LMF algorithm is proposed, which adopts an averaged gradient based step size as a self-adjusted step size. It is expected that the proposed algorithm also outperforms the conventional fixed step-size LMF. The superiority of the proposed algorithm is confirmed by the simulations in the time invariant and time variant channels.

• Journal of the Korean Society of Industry Convergence
• /
• v.7 no.4
• /
• pp.377-382
• /
• 2004

This research was about implementing STEP for data exchange among different commercial package(CAD system). STEP was used to share CAD data as follows. ST-Developer implement Solid model was used with a physical file of STEP and represented in a CAD system. And then STEP conversion utility was used to make a neutrality format form in a component modeling. Analysis of Solid model was made possible for CAD system to read in and analyzed Solid model. This research are summarized as follows 1. A basis Model development used Visual C++ for a neutrality data of a programming interface general-use CAD system, and produced Box and Cylinder to a physical file, the result was implemented this in a programming interface to general-use CAD system, it is represented in CAD system as identical one modeling object. 2. STEP was used in different CAD system to utilize to its of each CAD system maximum, CATIA V5R9 user was able to analyze MDT 6 Modeling Arm. 3. STEP was used able to interpret and remodel the existing Solid model.

• Korean Journal of Computational Design and Engineering
• /
• v.12 no.1
• /
• pp.8-14
• /
• 2007

In the product design process computer-aided engineering and optimization tolls are widely utilized in order to reduce the total development time and cost. Since several simulation tools are involved in the process, information losses, omissions, or errors are common and the importance of seamless information exchange among the tools has been increased. In this work, ISO STEP standards are adopted to represent the neutral format for structural analysis and optimization. The schema of AP209 defined the information of finite element analysis is used and the new schema is proposed to describe the information of structural optimization based on the STEP methodology. The schema is implemented by EXPRESS, information modeling language, and ST-Developer is employed to generate C++ classes and STEP Rose Library by using the schema denoted. To substantiate the proposed approach, the information access interfaces of the finite element modeling software (FEMAP), structural optimization software(GENESIS) and in-house topology optimization program are developed. Examples are shown to validate the information exchange of finite element analysis and structural optimization using STEP standards.

• Proceedings of the KSME Conference
• /
• 2001.06e
• /
• pp.506-511
• /
• 2001

This paper presents how redevelopment of the boundary layer in a backward-facing step flow is affected by boundary conditions imposed on velocity at the inlet, top and exit of the flow. A two-dimensional, laminar, incompressible flow over a backward-facing step with an open top boundary has been computed by using numerical methods of second-order time and spatial accuracy and a fractional-step method that guarantees a divergence-free velocity field at all time. The inlet velocity profile above the step is of Blasius type. Along the top boundary, shear-tree and Dirichlet conditions on the streamwise velocity were considered and at the exit fully-developed and convective boundary conditions were examined. (The vertical velocity at all boundaries were assumed to be zero explicitly or implicitly.) From the computed flow fields, the reattachment on the bottom side of shear layer separated from the tip of the step and succeeding redevelopment of the boundary layer were investigated.

• Proceedings of the Korean Geotechical Society Conference
• /
• 2001.10c
• /
• pp.103-122
• /
• 2001

For prediction of ground movement per the excavation step, observational results of ground movement during the construction was very different with prediction during the analysis of design. step because of the uncertainty of the numerical analysis modelling, the soil parameter, and the condition of a construction field, etc. however accuratly numerical analysis method was applied. Therefore, the management system through the construction field measurement should be achieved for grasping the situation during the excavation. Until present, the measurement system restricted by ‘Absolute Value Management system’only analyzing the stability of present step was executed. So, it was difficult situation to expect the prediction of ground movement for the next excavation step. In this situation, it was developed that ‘The Management system TOMAS-EXCAV’ consisted of ‘Absolute value management system’ analyzing the stability of present step and ‘Prediction management system’ expecting the ground movement of next excavation step and analyzing the stability of next excavation step by‘Back Analysis’. TOMAS-EXCAV could be applied to all uncertainty of earth retaining structures analysis by connecting ‘Forward analysis program’ and ‘Back analysis program’ and optimizing the main design variables using SQP-MMFD optimization method through measurement results. The application of TOMAS-EXCAV was confirmed that verifed the three earth retaing construction field by back analysis.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.15 no.1
• /
• pp.22-28
• /
• 2015

This paper proposes column-parallel three step Single Slope Analog-to-Digital Converter (SS-ADC) for high frame rate VGA CMOS Image Sensors (CISs). The proposed three step SS-ADC improves the sampling rate while maintaining the architecture of the conventional SS-ADC for high frame rate CIS. The sampling rate of the three-step ADC is increased by a factor of 39 compared with the conventional SS-ADC. The proposed three-step SS-ADC has a 12-bit resolution and 200 kS/s at 25 MHz clock frequency. The VGA CIS using three step SS-ADC has the maximum frame rate of 200 frames/s. The total power consumption is 76 mW with 3.3 V supply voltage without ramp generator buffer. A prototype chip was fabricated in a $0.13{\mu}m$ CMOS process.