• PNF and Movement
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• 제4권1호
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• pp.51-62
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• 2006

Purpose : The purposes of this study were to test the effect of proprioceptive and vestibular sensory input on expression of BDNF after traumatic brain injury in the rat. Subject : The control group was sacrificed at 24 hours after traumatic brain injury. The experimental group I was housed in standard cage for 7 days. The experimental group II was housed in standard cage after intervention to proprioceptive and vestibular sensory(balance training) for 7 days. Method : Traumatic brain injury was induced by weight drop model and after operation they were housed in individual standard cages for 24 hours. After 7th day, rats were sacrificed and cryostat coronal sections were processed individual1y in goat polyclonal anti-BDNF antibody. The morphologic characteristics and the BDNF expression were investigated in injured hemisphere section and contralateral brain section from immunohistochemistry using light microscope. Result : The results of this experiment were as follows: 1. In control group, cell bodies in lateral nucleus of cerebellum, superior vestibular nucleus, purkinje cell layer of cerebellum and pontine nucleus changed morphologically. 2. The expression of BDNF in contralateral hemisphere of group II were revealed. 3. On 7th day after operation, immunohistochemical response of BDNF in lateral nucleus, superior vestibular nucleus, purkinje cell layer and pontine nucleus appeared in group II. Conclusion : The present results revealed that intervention to proprioceptive and vestibular sensory input is enhance expression of BDNF and it is useful in neuronal reorganization improvement after traumatic brain injury.

• 전기학회논문지P
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• 제58권4호
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• pp.597-601
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• 2009

Green car such as a hybrid electrical vehicle and fuel cell vehicle is developed as a commercial target. UN/ECE/WP29 is developing GTR of HFCV and establishing the regulation and standard of electrical safety by ELSA. The regulation and standard about Electrical safety of vehicle are prescribed in ISO, UN/ECE, FMVSS, Japanese Attachment and so on, in case of insulation resistance is referred to keep more than 100/Vdc, 500/Vac. However, accurate method to measure insulation resistance agreeable to structure of vehicle does not exist now, it is actually that correctness of measurement drops according to the feature of battery and fuel cell stack. In this paper, the method to measure insulation resistance for protection against electrical shock by direct contact or indirect contact in Green Car will be indicated by making a comparison between the insulation measurement in standard of electrical safety and the experiment results for HEV and HFCV.

• 한국전기전자재료학회논문지
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• 제19권11호
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• pp.994-999
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• 2006

For low-cost embedded EEPROM, in this paper, single polysilicon EEPROM and n-channel high-voltage LDMOST device are developed in a $0.25{\mu}m$ standard CMOS logic process. Using these devices developed, the EEPROM chip is fabricated. The fabricated EEPROM chip is composed of 1 Kbit single polysilicon EEPROM away and high voltage driver circuits. The program and erase characteristics of the fabricated EEPROM chip are evaluated using 'STA-EL421C'. The fabricated n-channel high-voltage LDMOST device operation voltage is over 10 V and threshold voltage window between program and erase states of the memory cell is about 2.0 V.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제7권2호
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• pp.288-307
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• 2013

This paper formulates resource allocation for decode-and-forward (DF) relay assisted multi-cell orthogonal frequency division multiple (OFDM) networks as an optimization problem taking into account of inter-cell interference and users fairness. To maximize the transmit rate of system we propose a joint interference coordination, subcarrier and power allocation algorithm. To reduce the complexity, this semi-distributed algorithm divides the primal optimization into three sub-optimization problems, which transforms the mixed binary nonlinear programming problem (BNLP) into standard convex optimization problems. The first layer optimization problem is used to get the optimal subcarrier distribution index. The second is to solve the problem that how to allocate power optimally in a certain subcarrier distribution order. Based on the concept of equivalent channel gain (ECG) we transform the max-min function into standard closed expression. Subsequently, with the aid of dual decomposition, water-filling theorem and iterative power allocation algorithm the optimal solution of the original problem can be got with acceptable complexity. The third sub-problem considers dynamic co-channel interference caused by adjacent cells and redistributes resources to achieve the goal of maximizing system throughput. Finally, simulation results are provided to corroborate the proposed algorithm.

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2011년도 춘계학술대회 초록집
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• pp.100.1-100.1
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• 2011

Electrochemical impedance spectroscopy(EIS) are using widely as a useful technique mainly in the field of electrochemical for the analysis of electrode reactions or characteristics of the composites. The response analysis of the systems technique provides comprehensive informations about the characteristic and structure of complex and internal reaction. The EIS is the method to measure impedance of the measurement target classified by the frequency, it select the equivalent impedance model to give same response from the result and it calculate the parameter. Therefore, the chemical reaction inside the fuel cell is to modeling to electrical impedance. And as repeating the same experiment in each of the operating point, we can get each different parameter. As a result, we can establish the equivalent impedance model in each operating point. Therefore, if we use these models, we can evaluate the fuel cell without the internal design parameter of the fuel cell as required in existing modeling. The EIS is used typically technique for distinguish status of fuel cell called SOH(State Of Health). When the fuel cell is degradation, Efficiency and health of the fuel cell is reduced because internal impedance is increase. As usage of these principles, we can evaluate state of fuel cell through the impedance analysis of fuel cells. In this study, we are presents EIS distinction system and algorithm for residential fuel cell systems. At the time of the fuel cell installation in the fields, the EIS system and proposed algorithm will be able to apply as technique for efficiency and performance evaluation about fuel cell system.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제55권8호
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• pp.399-403
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• 2006

An accurate constant output voltage provided by the analog memory cell may be used by the low power oscillator to generate an accurate low frequency output signal. This accurate low frequency output signal may be used to maintain long-term timing accuracy in host devices during sleep modes of operation when an external crystal is not available to provide a clock signal. Further, incorporation of the analog memory cell in the low power oscillator is fully implementable in a 0.35um Samsung standard CMOS process. Therefore, the analog memory cell incorporated into the low power oscillator avoids the previous problems in a oscillator by providing a temperature-stable, low power consumption, size-efficient method for generating an accurate reference clock signal that can be used to support long sleep mode operation.

• 한국기계가공학회지
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• 제10권5호
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• pp.58-64
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• 2011

In this paper, research on the manufacturing technology of hexagonal structure core is investigated. Also the optimal forming process of the honeycomb core is developed and the rolling process is analyzed using finite element code, $DEFORM^{TM}$-3D. The standard honeycomb has a uniform hexagonal structure defined by the material, cell size, cell wall thickness and bulk density. Honeycomb core products can be made from any thin, flat material. The most common cell configuration is the hexagon but there are many other shapes for special applications. Because of the precision shape and the thin thickness, the honeycomb core is not easy to manufacture in the metal forming process. Through this study it was confirmed that after the rolling process, the section of honeycomb close to the standard shape can be obtained. This result is reflected to the manufacturing process design for the honeycomb core.

• 대한전자공학회논문지
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• 제24권6호
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• pp.1049-1055
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• 1987

This paper describes a near-optimal standard cell layout strategy which consists of three consecutives steps` partition, placement, and routing. In the partition step, a given network is torn apart into many subnetworks such that each subnetworks contains as many cells as possible with minimum interocnnections between subnetwork. In the placement step, the conventional string placement algorithm was modified. Also, bonding pads were placed such that their connections to the related cells are shortest. As a result for the tested example, the placement time was saved by 60% and the total routing lengths were saved by more than 20% and substantial improvements in the number of feed-through cell and the track density were obtained. The layout program is coded in PASCAL and implemented on a VAX 11-750/UNIX computer.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 심포지엄 논문집 정보 및 제어부문
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• pp.66-68
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• 2006

DVB-H (Digital Video Broadcasting for Handhold) is a new standard, currently being developed, which defines mobile enhancements for the DVB-T (DVB-Terrestrial) standard. For the reception of service via mobile handhold devices, seamless mobility and power saving are essential requirements of DVB-H. For seamless handover, the receiver should monitor neighboring cells and it increases the power consumption. And so, power efficient handover scheme to support both mobility and power saving is required. In this paper, we propose cell searching scheme to reduce power consumption by reducing the number of frequency scanning during the handover. Through the numerical evaluation, we analyzethe performance of handover schemes.

• 전자공학회논문지A
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• 제31A권6호
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• pp.199-208
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• 1994

This paper proposes a delay fault test technique for ICs and PCBs with the boundary-scan architectures supporting ANSI/IEEE Std 1149.1-1990. The hybrid delay fault model, which comprises both of gate delay faults and path delay faults, is selected. We developed a procedure for testing delay faults in the circuits with typical boundary scan cells supporting the standard. Analyzing it,we concluded that it is impractical because the test clock must be 2.5 times faster than the system clock with the cell architect-ures following up the state transition of the TAP controller and test instruction set. We modified the boundary-scan cell and developed test instructions and the test procedure. The modified cell and the procedure need test clock two times slower than the system clock and support the ANSI/IEEE standard perfectly. A 4-bit ALU is selected for the circuits under test. and delay tests are simulated by the SILOS simulator. The simulation results ascertain the accurate operation and effectiveeness of the modified mechanism.