• Journal of KIISE:Computing Practices and Letters
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• v.16 no.2
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• pp.177-185
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• 2010

Ray-object intersection is an important element in ray tracing that takes up a substantial amount of computing time. In general, such spatial data structure as kd-tree has been frequently used for static scenes to accelerate the intersection computation. Recently, a few variants of kd-tree traversal have been proposed suitable for the GPU that has a relatively restricted computing architecture compared to the CPU. In this article, we propose yet another two implementation techniques that can improve those previous ones. First, we present a cached stack method that is aimed to reduce the costly global memory access time needed when the stack is allocated to global memory. Secondly, we present a rope-with-short-stack method that eases the substantial memory requirement, often necessary for the previous rope method. In order to show the effectiveness of our techniques, we compare their performances with those of the previous GPU traversal methods. The experimental results will provide prospective GPU ray tracer developers with valuable information, helping them choose a proper kd-tree traversal method.

• Journal of Advanced Navigation Technology
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• v.12 no.5
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• pp.420-428
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• 2008

In this paper, Stack structure patch antenna has been designed and fabricated for wireless LAN applications. The patch and ground plane were used by PEC metal. It was 0.05 [mm] thick. In order to broaden the bandwidth of the antenna and improve of gain, the stack structured antenna with probe feed. The measured input return loss showed less than -10 [dB] at the broadband from 5100 to 6140 [MHz]. It's measured bandwidth was 1040 MHz. The gain of antenna in the E-plane and H-plane was 13 dBi and 3 dB beam width was $40^{\circ}$.

• Korean Journal of Materials Research
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• v.23 no.3
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• pp.206-210
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• 2013

In the segmented-in-series solid-oxide fuel cells (SIS-SOFCs), fabrication techniques which use decalcomania paper have many advantages, i.e., an increased active area of the electrode; better interfacial adhesion property between the anode, electrolyte and cathode; and improved layer thickness uniformity. In this work, a cell-stack was fabricated on porous ceramic flattened tube supports using decalcomania paper, which consists of an anode, electrolyte, and a cathode. The anode layer was $40{\mu}m$ thick, and was porous. The electrolyte layers exhibited a uniform thickness of about $20{\mu}m$ with a dense structure. Interfacial adhesion was improved due to the dense structure. The cathode layers was $30{\mu}m$ thick with porous structure, good adhesion to the electrolyte. The ohmic resistance levels at 800, 750 and $700^{\circ}C$ were measured, showing values of 1.49, 1.58 and $1.65{\Omega}{\cdot}cm^2$, respectively. The polarization resistances at 800, 750 and $700^{\circ}C$ were measured to be 1.63, 2.61 and $4.17cm^2$, respectively. These lower resistance values originated from the excellent interfacial adhesion between the anode, electrolyte and cathode. In a two-cell-stack SOFC, open-circuit voltages(OCVs) of 1.915, 1.942 and 1.957 V and maximum power densities(MPD) of 289.9, 276.1 and $220.4mW/cm^2$ were measured at 800, 750 and $700^{\circ}C$, respectively. The proposed fabrication technique using decalcomania paper was shown to be feasible for the easy fabrication of segmented-in-series flattened tube SOFCs.

• Transactions of the Korean hydrogen and new energy society
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• v.23 no.5
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• pp.468-475
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• 2012

A proper stacking force and assembly are important to the performance of fuel cell. Improper assembly pressure may lead to leakage of fuels and high interfacial contact resistance, excessive assembly pressure may result in damage to the gas diffusion layer and other components. The pressure distribution of gas diffusion layer is important to make interfacial contact resistance less for stack performance. To analyze the influence of design parameter factors for pressure distribution, and to optimize stack design, DOE (Design of Experiment) was used for polymer electrolyte membrane fuel cell stack pressure test. As commonly known, the higher clamping force improves the fuel cell stack performance. However, non-uniformity of stress distribution is also increased. It shows that optimization between clamping force and stress distribution is needed for well designed structure of fuel cell stack. In this study, stack design optimization method is suggested by using FEM (Finite Element Methode) and DOE for light-weighted fuel cell stack.

• Proceedings of the Korea Committee for Ocean Resources and Engineering Conference
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• 2000.10a
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• pp.84-89
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• 2000

Thermal simulation of typical stack-type and newly proposed planar-type micro-gas sensors were studied by FEM method. The thermal analyses for the proposed planar structure including temperatur distribution over the sensing layer and power consumption of the heater were carried using finite element method by computer simulation and well compared with those of typical stack-type micro-gas sensor. The thermal properties of the microsensor from thermal simulation were compared with those of a actual device to investigate the acceptability of the computer simulation.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2007.04a
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• pp.37-47
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• 2007

Factor : Structure Metal pad & SMO size Board level TC test : - Large SMO size better Board level Drop test : - Large SMO size better Factor : Structure Substrate thickness Board level TC test : - Thick substrate better Board level Drop test : - Substrate thickness is not a significant factor for drop test Factor : Material Solder alloy Board level TC test : - Not so big differences over Pb-free solder and NiAu, OSP finish Board level Drop test : - Ni/Au+SAC105, CuOSP+LF35 are better Factor : Material Pad finish Board level TC test : - NiAu/NiAu is best Board livel Drop test : - CuOSP is best Factor : Material Underfill Board level TC test - Several underfills (reworkable) are passed TCG x500 cycles Board level Drop test : - Underfill lots have better performance than non-underfill lots Factor : Process Multiple reflow Board level TC test : - Multiple reflow is not a significant actor for TC test Board level Drop test : N/A Factor : Process Peak temp Board level TC test : - Higher peak temperature is worse than STD Board level Drop test : N/A Factor : Process Stack method Board level TC test : - No big difference between pre-stack and SMT stack Board level Drop test : - Flux dipping is better than paste dipping but failure rate is more faster

• International journal of advanced smart convergence
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• v.9 no.3
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• pp.253-259
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• 2020

Most of today's large-scale cloud systems and enterprise data centers are distributing resources to improve scalability and resource utilization. NVMe-over-Fabric protocol allows submitting NVMe commands to a remote NVMe SSD through RDMA (Remote Direct Memory Access) network. It is attracting attention recently because it is possible to construct a disaggregation storage system with low latency through the protocol. However, the current I/O stack of NVMe-over-Fabric has an inefficient structure for maintaining compatibility with the traditional I/O stack. Therefore, in this paper, we propose a new mechanism to reduce I/O latency and CPU overhead by modifying I/O path of NVMe-over-Fabric to pass through legacy block layer. According to the performance evaluation results, the proposed mechanism is able to reduce the I/O latency and CPU overhead by up to 22% and 24% compared to the existing NVMe-over-Fabrics protocol, respectively.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.927-930
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• 2003

In this paper, a design of processor IP for TCP/IP protocol stack is described. The processor consists of input and output buffer memory with dual bank structure, 32-bit RISC microprocessor core, DMA unit with on-the-fly checksum capability. To handle the various modes of TCP/IP protocol, hardware and software co-design approach is used rather than the conventional state machine based design. To eliminate delay time due to the data transfer and checksum operation, DAM module which can execute the checksum operation on-the-fly along with data transfer operation is adopted. By programming the on-chip code ROM of RISC processor differently. the designed stack processor can support the packet format conversion operations required in the various TCP/IP protocols.

• Convergence Security Journal
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• v.5 no.4
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• pp.19-25
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• 2005

Threaded Tree is the data structure that can express parse stack as well as parse tree with LR parsing table. $Larchev\^{e}que$ makes Threaded Tree and Incremental Parsing with stack. This paper suggests the algorithm consisting of changed threaded tree without stack in order to reduce reparsing node and parsing speed. Also, it suggests incremental parsing algorithm to get rid of the reparsing process in node.

• Proceedings of the KIPE Conference
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• 2005.07a
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• pp.507-510
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• 2005

High voltage pulse power supply using Marx generator and solid-state switches is proposed in this study. The Marx generator is composed of 12 stages and each stage is made of IGBT stack, two diode stacks, and capacitor. To charge the capacitors of each stage in parallel, inductive charging method is used and this method results in high efficiency and high repetition rates. It can generate the pulse voltage with the following parameters: Voltage: up to 120kv Rising time: sub ${\mu}S$ Pulse width: up to $10{\mu}S$, Pulse repetition rate: 1000pps The proposed pulsed power generator uses IGBT stack with a simple driver and has modular design. So this system structure gives compactness and easiness to implement total system. Some experimental results are included to verify the system performances in this paper.