• 제목/요약/키워드: spiking neural network

검색결과 27건 처리시간 0.032초

ONNX기반 스파이킹 심층 신경망 변환 도구 (Conversion Tools of Spiking Deep Neural Network based on ONNX)

  • 박상민;허준영
    • 한국인터넷방송통신학회논문지
    • /
    • 제20권2호
    • /
    • pp.165-170
    • /
    • 2020
  • 스파이킹 신경망은 기존 신경망과 다른 메커니즘으로 동작한다. 기존 신경망은 신경망을 구성하는 뉴런으로 들어오는 입력 값에 대해 생물학적 메커니즘을 고려하지 않은 활성화 함수를 거쳐 다음 뉴런으로 출력 값을 전달한다. 뿐만 아니라 VGGNet, ResNet, SSD, YOLO와 같은 심층 구조를 사용한 좋은 성과들이 있었다. 반면 스파이킹 신경망은 기존 활성화함수 보다 실제 뉴런의 생물학적 메커니즘과 유사하게 동작하는 방식이지만 스파이킹 뉴런을 사용한 심층구조에 대한 연구는 기존 뉴런을 사용한 심층 신경망과 비교해 활발히 진행되지 않았다. 본 논문은 기존 뉴런으로 만들어진 심층 신경망 모델을 변환 툴에 로드하여 기존 뉴런을 스파이킹 뉴런으로 대체하여 스파이킹 심층 신경망으로 변환하는 방법에 대해 제안한다.

DVS 카메라를 이용한 Spiking Neural Network 시뮬레이션을 위한 인터페이스 개발 (Implementing Interface for Spiking Neural Network Simulation for DVS Camera)

  • 권용인;허인구;이종원;백윤흥
    • 한국정보처리학회:학술대회논문집
    • /
    • 한국정보처리학회 2011년도 추계학술발표대회
    • /
    • pp.15-17
    • /
    • 2011
  • DVS 카메라는 인간의 눈을 모델링하여 만들어져서 화면의 변화에 반응하여 Address - Event - Representation 데이터를 생성하고 이 데이터는 jAER Viwer를 통해 확인할 수 있다. 이렇게 생성된 DVS 카메라의 데이터를 Spiking Neural Network의 입력으로 주기 위해 GPU를 이용한 Spiking Neural Network 시뮬레이터인 GPUSNN과 jAER 사이에 인터페이스가 필요하다. 이 인터페이스를 이용하면 GPUSNN을 통해 비전 알고리즘을 빠르고 효과적으로 Spiking Neural Network 시뮬레이션을 할 수 있을 것이다.

스파이킹 신경망 추론을 위한 심층 신경망 가중치 변환 (Deep Neural Network Weight Transformation for Spiking Neural Network Inference)

  • 이정수;허준영
    • 스마트미디어저널
    • /
    • 제11권3호
    • /
    • pp.26-30
    • /
    • 2022
  • 스파이킹 신경망은 실제 두뇌 뉴런의 작동원리를 적용한 신경망으로, 뉴런의 생물학적 메커니즘으로 인해 기존 신경망보다 학습과 추론에 소모되는 전력이 적다. 최근 딥러닝 모델이 거대해지며 운용에 소모되는 비용 또한 기하급수적으로 증가함에 따라 스파이킹 신경망은 합성곱, 순환 신경망을 잇는 3세대 신경망으로 주목받으며 관련 연구가 활발히 진행되고 있다. 그러나 스파이킹 신경망 모델을 산업에 적용하기 위해서는 아직 선행되어야 할 연구가 많이 남아있고, 새로운 모델을 적용하기 위한 모델 재학습 문제 역시 해결해야 한다. 본 논문에서는 기존의 학습된 딥러닝 모델의 가중치를 추출하여 스파이킹 신경망 모델의 가중치로 변환하는 것으로 모델 재학습 비용을 최소화하는 방법을 제안한다. 또한, 변환된 가중치를 사용한 추론 결과와 기존 모델의 결과를 비교해 가중치 변환이 올바르게 작동함을 보인다.

Spiking Neural Networks(SNN) 구조에서 뉴런의 개수와 학습량에 따른 학습 성능 변화 분석 (An analysis of learning performance changes in spiking neural networks(SNN))

  • 김용주;김태호
    • 문화기술의 융합
    • /
    • 제6권3호
    • /
    • pp.463-468
    • /
    • 2020
  • 인공지능 연구는 다양한 분야에 적용되며 발전하고 있다. 본 논문에서는 차세대 인공지능 연구 분야인 SNN(Spiking Neural Networks) 형태의 인공지능 구현 방식을 사용하여 신경망을 구축하고, 그 신경망에서 뉴런의 개수가 신경망의 성능에 어떠한 영향을 미치는지를 분석한다. 또한 신경망 학습량을 증가시키면서 신경망의 성능이 어떻게 바뀌는지를 분석한다. 해당 연구 결과를 통해 각 분야에서 사용되는 SNN 기반의 신경망을 최적화 할 수 있을 것이다.

The Excitability by Both Electric and Concentrative Perturbation in CSTR

  • Bae, Jeong Min;Cho, Ung In
    • Bulletin of the Korean Chemical Society
    • /
    • 제27권8호
    • /
    • pp.1145-1148
    • /
    • 2006
  • Excitability is one of the basic and fundamental mechanisms utilized for signal transmission in living organisms. With reference to the condition by Marek and the condition by Schneider, we found a condition in which excitability with similar shapes can appear by chemical and electric perturbation. Our condition is constructed with 3 chemical channels and 1 electric channel, and can be used as a condition for a chemical spiking neuron and as a unit of a chemical spiking neural network.

A Novel Spiking Neural Network for ECG signal Classification

  • Rana, Amrita;Kim, Kyung Ki
    • 센서학회지
    • /
    • 제30권1호
    • /
    • pp.20-24
    • /
    • 2021
  • The electrocardiogram (ECG) is one of the most extensively employed signals used to diagnose and predict cardiovascular diseases (CVDs). In recent years, several deep learning (DL) models have been proposed to improve detection accuracy. Among these, deep neural networks (DNNs) are the most popular, wherein the features are extracted automatically. Despite the increment in classification accuracy, DL models require exorbitant computational resources and power. This causes the mapping of DNNs to be slow; in addition, the mapping is challenging for a wearable device. Embedded systems have constrained power and memory resources. Therefore full-precision DNNs are not easily deployable on devices. To make the neural network faster and more power-efficient, spiking neural networks (SNNs) have been introduced for fewer operations and less complex hardware resources. However, the conventional SNN has low accuracy and high computational cost. Therefore, this paper proposes a new binarized SNN which modifies the synaptic weights of SNN constraining it to be binary (+1 and -1). In the simulation results, this paper compares the DL models and SNNs and evaluates which model is optimal for ECG classification. Although there is a slight compromise in accuracy, the latter proves to be energy-efficient.

A Spiking Neural Network for Autonomous Search and Contour Tracking Inspired by C. elegans Chemotaxis and the Lévy Walk

  • Chen, Mohan;Feng, Dazheng;Su, Hongtao
    • KSII Transactions on Internet and Information Systems (TIIS)
    • /
    • 제16권9호
    • /
    • pp.2846-2866
    • /
    • 2022
  • Caenorhabditis elegans exhibits sophisticated chemotaxis behavior through two parallel strategies, klinokinesis and klinotaxis, executed entirely by a small nervous circuit. It is therefore suitable for inspiring fast and energy-efficient solutions for autonomous navigation. As a random search strategy, the Lévy walk is optimal for diverse animals when foraging without external chemical cues. In this study, by combining these biological strategies for the first time, we propose a spiking neural network model for search and contour tracking of specific concentrations of environmental variables. Specifically, we first design a klinotaxis module using spiking neurons. This module works in conjunction with a klinokinesis module, allowing rapid searches for the concentration setpoint and subsequent contour tracking with small deviations. Second, we build a random exploration module. It generates a Lévy walk in the absence of concentration gradients, increasing the chance of encountering gradients. Third, considering local extrema traps, we develop a termination module combined with an escape module to initiate or terminate the escape in a timely manner. Experimental results demonstrate that the proposed model integrating these modules can switch strategies autonomously according to the information from a single sensor and control steering through output spikes, enabling the model worm to efficiently navigate across various scenarios.

FPGA Implementation of an Artificial Intelligence Signal Recognition System

  • Rana, Amrita;Kim, Kyung Ki
    • 센서학회지
    • /
    • 제31권1호
    • /
    • pp.16-23
    • /
    • 2022
  • Cardiac disease is the most common cause of death worldwide. Therefore, detection and classification of electrocardiogram (ECG) signals are crucial to extend life expectancy. In this study, we aimed to implement an artificial intelligence signal recognition system in field programmable gate array (FPGA), which can recognize patterns of bio-signals such as ECG in edge devices that require batteries. Despite the increment in classification accuracy, deep learning models require exorbitant computational resources and power, which makes the mapping of deep neural networks slow and implementation on wearable devices challenging. To overcome these limitations, spiking neural networks (SNNs) have been applied. SNNs are biologically inspired, event-driven neural networks that compute and transfer information using discrete spikes, which require fewer operations and less complex hardware resources. Thus, they are more energy-efficient compared to other artificial neural networks algorithms.

SNN eXpress: Streamlining Low-Power AI-SoC Development With Unsigned Weight Accumulation Spiking Neural Network

  • Hyeonguk Jang;Kyuseung Han;Kwang-Il Oh;Sukho Lee;Jae-Jin Lee;Woojoo Lee
    • ETRI Journal
    • /
    • 제46권5호
    • /
    • pp.829-838
    • /
    • 2024
  • SoCs with analog-circuit-based unsigned weight-accumulating spiking neural networks (UWA-SNNs) are a highly promising solution for achieving lowpower AI-SoCs. This paper addresses the challenges that must be overcome to realize the potential of UWA-SNNs in low-power AI-SoCs: (i) the absence of UWA-SNN learning methods and the lack of an environment for developing applications based on trained SNN models and (ii) the inherent issue of testing and validating applications on the system being nearly impractical until the final chip is fabricated owing to the mixed-signal circuit implementation of UWA-SNN-based SoCs. This paper argues that, by integrating the proposed solutions, the development of an EDA tool that enables the easy and rapid development of UWA-SNN-based SoCs is feasible, and demonstrates this through the development of the SNN eXpress (SNX) tool. The developed SNX automates the generation of RTL code, FPGA prototypes, and a software development kit tailored for UWA-SNN-based application development. Comprehensive details of SNX development and the performance evaluation and verification results of two AI-SoCs developed using SNX are also presented.

Asynchronous interface circuit for nonlinear connectivity in multicore spiking neural networks

  • Sung-Eun Kim;Kwang-Il Oh;Taewook Kang;Sukho Lee;Hyuk Kim;Mi-Jeong Park;Jae-Jin Lee
    • ETRI Journal
    • /
    • 제46권5호
    • /
    • pp.878-889
    • /
    • 2024
  • To expand the scale of spiking neural networks (SNNs), an interface circuit that supports multiple SNN cores is essential. This circuit should be designed using an asynchronous approach to leverage characteristics of SNNs similar to those of the human brain. However, the absence of a global clock presents timing issues during implementation. Hence, we propose an intermediate latching template to establish asynchronous nonlinear connectivity with multipipeline processing between multiple SNN cores. We design arbitration and distribution blocks in the interface circuit based on the proposed template and fabricate an interface circuit that supports four SNN cores using a full-custom approach in a 28-nm CMOS (complementary metal-oxide-semiconductor) FDSOI (fully depleted silicon on insulator) process. The proposed template can enhance throughput in the interface circuit by up to 53% compared with the conventional asynchronous template. The interface circuit transmits spikes while consuming 1.7 and 3.7 pJ of power, supporting 606 and 59 Mevent/s in intrachip and interchip communications, respectively.