• The KIPS Transactions:PartA
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• v.15A no.4
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• pp.217-226
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• 2008

Branch prediction accuracy is critical for system performance in modern microprocessor architectures. The use of speculative update branch history provides substantial accuracy improvement in branch prediction. However, speculative update branch history is the information about uncommitted branch instruction and thus it may hurts program correctness, in case of miss-speculative execution. Therefore, speculative update branch history requires suitable recovery mechanisms to provide program correctness as well as performance improvement. In this paper, we propose recovery logics for speculative update branch history. The proposed solutions are recovery logics for both global history and local history. In simulation results, our solution provides performance improvement up to 5.64%. In addition, it guarantees the program correctness and almost 90% of additional hardware overhead is reduced, compared to previous works.

• Proceedings of the Korean Information Science Society Conference
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• 2001.04a
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• pp.13-15
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• 2001

슈퍼스칼라 프로세서에서 값 예측기는 한 명령어의 결과를 미리 예측하여 명령들 간의 데이터 종속관계를 극복하고 실행함으로써 명령어 수준 병렬성 (Instruction Level Parallesim, ILP)을 향상시키는 기법이다. 최근의 값 예측기는 프로세서의 명령 이슈율이 커짐에 따라 예측 테이블의 갱신이 테이블의 참조 속도를 따라가지 못하여 예측기의 성능이 저하되는 경향이 있다. 본 논문에서는 이러한 성능저하를 줄이기 위해 명령의 결과가 나올 때까지 기다리지 않고 테이블 값을 모험적으로 갱신(speculative update)하는 스트라이드 값 예측기를 제안한다. 제안된 방식의 타당성을 검증하기 위해 SimpleScalar 시뮬레이터 상에 제안된 예측기를 구현하여 SPECint95 벤치마트를 시뮬레이션하고 제안된 스트라이드 모험적 갱신(stride speculative update)이 기존의 스트라이드 예측기 보다 성능이 향상됨을 보인다.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.11
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• pp.592-600
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• 2001

To improve the performance of wide-issue Superscalar microprocessors, it is essential to increase the width of instruction fetch and issue rate. Data dependences are major hurdle to exploit ILP(Instruction-Level Parallelism) efficiently, so several related works have suggested that the limits imposed by data dependences can be overcome to some extent with the use of the data value prediction. But the suggested mechanisms may access the same value prediction table entry again before they have been updated with a real data value. They will cause incorrect value prediction by using stable data and incur misprediction penalty and lowering performance. In this paper, we propose a new hybrid value predictor which achieve high performance by reducing stale data. Because the proposed hybrid value predictor can update the prediction table speculatively, it efficiently reduces the number of mispredicted instruction due to stable due to stale data. For SPECint95 benchmark programs on the 16-issue superscalar processors, simulation results show that the average prediction accuracy increase from 59% for non-speculative update to 72% for speculative update.

• Proceedings of the Korean Information Science Society Conference
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• 2000.10c
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• pp.639-641
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• 2000

슈퍼스칼라 프로세서는 성능향상을 위해 명령어 반입 폭과 이슈 폭을 증가시키고 있다. 최근 여러 논문들에서 데이터 종속성을 제거하기 위해서 명령어의 결과 값을 예상하는 메커니즘이 연구되었다. 그러나 그러한 예측기들은 예상한 명령어의 실제 결과 값으로 예상 테이블을 갱신하기 전에 그 명령어를 다시 예상할 때 예상 실패율이 증가하여 프로세서의 성능을 감소시킨다. 본 논문에서는 비 순서적(out-of-order)으로 이슈 및 실행하는 프로세서에서 예상 적중율을 향상시키기 위해 명령어 반입 시 결과 값을 예상하는 동시에 예측기 테이블을 모험적으로 갱신(Speculative update)하는 하이브리드 결과 값 예측기를 제안한다. 본 논문에서 제안한 모험적 갱신이 예상 적중률을 향상시킬 수 있음을 보이기 위해 SimpleScalar 3.0 툴 셋을 사용하여 SPECint95 벤치마크 프로그램에서 명령어를 예상한 후 결과가 구해져서 예상테이블을 수정하기 전에 그 명령어를 다시 예상하는 빈도수를 측정하였다.

• Agribusiness and Information Management
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• v.1 no.2
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• pp.43-60
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• 2009

To improve the performance of wide-issue superscalar processors, it is essential to increase the width of instruction fetch and the issue rate. Removal of control hazard has been put forward as a significant new source of instruction-level parallelism for superscalar processors and the conditional branch prediction is an important technique for improving processor performance. Branch mispredictions, however, waste a large number of cycles, inhibit out-of-order execution, and waste electric power on mis-speculated instructions. Hence, the branch predictor with higher accuracy is necessary for good processor performance. In global-history-based predictors like gshare and GAg, many mispredictions come from commit update of the branch history. Some works on this subject have discussed the need for speculative update of the history and recovery mechanisms for branch mispredictions. In this paper, we present a new mechanism for recovering the branch history after a misprediction. The proposed mechanism adds an age_counter to the original predictor and doubles the size of the branch history register. The age_counter counts the number of outstanding branches and uses it to recover the branch history register. Simulation results on the SimpleScalar 3.0/PISA tool set and the SPECINT95 benchmarks show that gshare and GAg with the proposed recovery mechanism improved the average prediction accuracy by 2.14% and 9.21%, respectively and the average IPC by 8.75% and 18.08%, respectively over the original predictor.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.6
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• pp.306-313
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• 2005

Conditional branch prediction is an important technique for improving processor performance. Branch mispredictions, however, waste a large number of cycles, inhibit out-of-order execution, and waste electric power on mis-speculated instructions. Hence, the branch predictor with higher accuracy is necessary for good processor performance. In global-history-based predictors like gshare and GAg, many mispredictions come from commit update of the history. Some works on this subject have discussed the need for speculative update of the history and recovery mechanisms for branch mispredictions. In this paper, we present a simple mechanism for recovering the branch history after a misprediction. The proposed mechanism adds an age_counter to the original predictor and doubles the size of the branch history register. The age_counter counts the number of outstanding branches and uses it to recover the branch history register. Simulation results on the Simplescalar 3.0/PISA tool set and the SPECINTgS benchmarks show that gshare and GAg with the proposed recovery mechanism improved the average prediction accuracy by 2.14$\%$ and 9.21$\%$, respectively and the average IPC by 8.75$\%$ and 18.08$\%$, respectively over the original predictor.

• Journal of KIISE:Computing Practices and Letters
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• v.8 no.1
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• pp.107-115
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• 2002

We propose a new hybrid value predictor which achieves high performance by combining several predictors. Because the proposed hybrid value predictor can update the prediction table speculatively, it efficiently reduces the number of mispredicted instructions due to stale data. Also, the proposed predictor can enhance the prediction accuracy and efficiently decrease the hardware cost of predictor, because it allocates instructions into the best-suited predictor during instruction fetch stage by using the information of static classification which is obtained from the profile-based compiler implementation. For the 16-issue superscalar processors, simulation results based on the SimpleScalar/PISA tool set show that we achieve the average prediction rates of 73% by using speculative update and the average prediction rates of 88% by adding static classification for the SPECint95 benchmark programs.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.11
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• pp.601-612
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• 2001

In superscalar processors, value prediction is a technique that breaks true data dependences by predicting the outcome of an instruction in order to exploit instruction level parallelism(ILP). A value predictor looks up the prediction table for the prediction value of an instruction in the instruction fetch stage, and updates with the prediction result and the resolved value after the execution of the instruction for the next prediction. However, as the instruction fetch and issue rates are increased, the same instruction is likely to fetch again before is has been updated in the predictor. Hence, the predictor looks up the stale value in the table and this mostly will cause incorrect value predictions. In this paper, a stride value predictor with the capability of speculative updates, which can update the prediction table speculatively without waiting until the instruction has been completed, is proposed. Also, the performance of the scheme is examined using Simplescalar simulator for SPECint95 benchmarks in which our value predictor is added.

• Proceedings of the Korean Information Science Society Conference
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• 2005.11a
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• pp.766-768
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• 2005

분기 영령어의 예측 정확도는 시스템 전체 성능에 중대한 영향을 미친다. 여러 분기 예측 방식 가운데 하나인 "분기 정보의 투기적 사용" 은 분기 명령어의 가장 최근 기록을 일관되게 사용할 수 있도록 도와줌으로 해서 분기 예측의 정확도 향상에 크게 기여한다. 하지만 이와 같은 기법은 미완료 분기에 대한 히스토리를 투기적으로 사용하는 방식이다. 따라서 사용되는 정보가 올바르지 못할 수 있으며, 이런 경우 적절한 복구 기법을 필요로 한다. 본 논문에서는 분기 정보의 투기적 사용에 대한 필요성과 효율적인 복구 기법을 제안한다. 제안된 기법은 이전 연구와 비교하여 상당한 하드웨어 요구량의 감소를 가져왔으며, 또한 프로그램 수행의 정확성을 해치지 않으면서 최대 $3.3\%$의 성능향상을 보였다.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.12
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• pp.724-735
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• 2003

In recent high-performance superscalar processors, the result value of an instruction is predicted to improve instruction-level parallelism by breaking data dependencies. Using those predicted values, instructions are speculatively executed and substantial performance can be gained. It, however, requires additional power consumption due to the frequent access and update of the value prediction table. In this paper, first, the trade-off between the performance improvement and the increased power consumption for value prediction is measured and analyzed. And, in order to reduce additional power consumption without performance loss, the technique of controlling speculative execution with confidence counter and predicting useful instructions is developed. Also, in order to prove the validity, a tool is developed that can simulate processor behavior at cycle-level and measure total energy consumption and power consumption per cycle.