• Korean Journal of Materials Research
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• v.17 no.2
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• pp.73-80
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• 2007

For the sub-65 nm CMOS process, it is necessary to develop a new silicide material and an accompanying process that allows the silicide to maintain a low sheet resistance and to have an enhanced thermal stability, thus providing for a wider process window. In this study, we have evaluated the property and unit process compatibility of newly proposed composite silicides. We fabricated composite silicide layers on single crystal silicon from $10nm-Ni_{1-x}Co_x/single-crystalline-Si(100),\;10nm-Ni_{1-x}Co_x/poly-crystalline-\;Si(100)$ wafers (x=0.2, 0.5, and 0.8) with the purpose of mimicking the silicides on source and drain actives and gates. Both the film structures were prepared by thermal evaporation and silicidized by rapid thermal annealing (RTA) from $700^{\circ}C\;to\;1100^{\circ}C$ for 40 seconds. The sheet resistance, cross-sectional microstructure, surface composition, were investigated using a four-point probe, a field emission scanning probe microscope, a field ion beam, an X-ray diffractometer, and an Auger electron depth profi1ing spectroscopy, respectively. Finally, our newly proposed composite silicides had a stable resistance up to $1100^{\circ}C$ and maintained it below $20{\Omega}/Sg$., while the conventional NiSi was limited to $700^{\circ}C$. All our results imply that the composite silicide made from NiCo alloy films may be a possible candidate for 65 nm-CMOS devices.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.691-694
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• 2013

This paper has presented the potential distribution for asymmetric double gate(DG) MOSFET, and sloved Poisson equation to obtain the analytical solution of potential distribution. The symmetric DGMOSFET where both the front and the back gates are tied together is three terminal device and has the same current controllability for front and back gates. Meanwhile the asymmetric DGMOSFET is four terminal device and can separately determine current controllability for front and back gates. To approximate with experimental values, we have used the Gaussian function as charge distribution in Poisson equation. The potential distribution has been observed for gate bias voltage and gate oxide thickness and channel doping concentration of the asymmetric DGMOSFET. As a results, we know potential distribution is greatly changed for gate bias voltage and gate oxide thickness, especially for gate to increase gate oxide thickness. Also the potential distribution for source is changed greater than one of drain with increasing of channel doping concentration.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.330-332
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• 2009

Highly stable bottom gate thin film transistors(TFTs) with a zinc indium tin oxide(Zn-In-Sn-O:ZITO) channel layer have been fabricated by rf-magnetron co-sputtering using a indium tin oxide(ITO:90/10), a tin oxide and a zinc oxide targets. The ZITO TFT (W/L=$40{\mu}m/20{\mu}m$) has a mobility of 24.6 $cm^2$/V.s, a subthreshold swing of 0.12V/dec., a turn-on voltage of -0.4V and an on/off ratio of >$10^9$. When gate field of $1.8{\times}10^5$ V/cm was applied with source-drain current of $3{\mu}A$ at $60^{\circ}C$, the threshold voltage shift was ~0.18 V after 135 hours. We fabricated AM-OLED driven by highly stable bottom gate Zn-In-Sn-O TFT array.

• Journal of IKEEE
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• v.17 no.2
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• pp.214-220
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• 2013

Small area LDO (Low drop-out) regulator with pass transistor using body-driven technique is presented in this paper. The body-driven technique can decrease threshold voltage (Vth) and increase the current ID flowing from drain to source in current. The technique is applied to the pass transistor to reduce size of area and maintain the same performance as conventional LDO regulator. A pass transistor using the technique can reduce its size by 5.5 %. The proposed LDO regulator works under the input voltage of 2.7 V ~ 4.5 V and provides up to 150mA load current for an output voltage range of 1.2 V ~ 3.3 V.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.7
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• pp.993-1000
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• 2018

This paper proposes a low-dropout voltage regulator(LDO) using self-cascode structure. The self-cascode structure was optimized by adjusting the channel length of the source-side MOSFET and applying a forward voltage to the body of the drain-side MOSFET. The self-cascode of the input differential stage of the error amplifier is optimized to give higher transconductance, but the self-cascode of the output stage is optimized to give higher output resistance, The proposed LDO using self-cascode structure was designed by a $0.18{\mu}m$ CMOS technology and simulated using SPECTRE. The load regulation of the proposed LDO regulator was 0.03V/A, whereas that of the conventional LDO was 0.29V/A. The line regulation of the proposed LDO regulator was 2.23mV/V, which is approximately three times improvement compared to that of the conventional LDO. The transient response of the proposed LDO regulator was 625ns, which is 346ns faster than that of the conventional LDO.

• Electrical & Electronic Materials
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• v.9 no.1
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• pp.30-37
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• 1996

Previously, crystallization of a-Si:H films on glass substrates were limited to anneal temperature below 600.deg. C, over 10 hours to avoid glass shrinkage. Our study indicates that the crystallization is strongly influenced by anneal temperature and weakly affected by anneal duration time. Because of the high temperature process and nonconducting substrate requirements for poly-Si TFTs, the employed substrates were limited to quartz, sapphire, and oxidized Si wafer. We report on poly-Si TFT's using high temperature anneal on a Si:H/Mo structures. The metal Mo substrate was stable enough to allow 1000.deg. C anneal. A novel TFT fabrication was achieved by using part of the Mo substrate as drain and source ohmic contact electrode. The as-grown a-Si:H TFT was compared to anneal treated poly-Si TFT'S. Defect induced trap states of TFT's were examined using the thermally stimulated current (TSC) method. In some case, the poly-Si grain boundaries were passivated by hydrogen. A-SI:H and poly-Si TFT characteristics were investigated using an inverted staggered type TFT. The poly -Si films were achieved by various anneal techniques; isothermal, RTA, and excimer laser anneal. The TFT on as grown a-Si:H exhibited a low field effect mobility, transconductance, and high gate threshold voltage. Some films were annealed at temperatures from 200 to >$1000^{\circ}C$ The TFT on poly-Si showed an improved $I_on$$I_off$ ratio of $10_6$, reduced gate threshold voltage, and increased field effect mobility by three orders. Inverter operation was examined to verify logic circuit application using the poly Si TFTs.

• Transactions on Electrical and Electronic Materials
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• v.1 no.4
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• pp.1-6
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• 2000

The mechanical strength of silicon carbide dose nor permit the use of diffusion as a means to achieve selective doping as required by most electronic devices. While epitaxial layers may be doped during growth, ion implantation is needed to define such regions as drain and source wells, junction isolation regions, and so on. Ion activation without an annealing cap results in serious crystal damage as these activation processes must be carried out at temperatures on the order of 1600$^{\circ}C$. Ion implanted silicon carbide that is annealed in either a vacuum or argon environment usually results in a surface morphology that is highly irregular due to the out diffusion of Si atoms. We have developed and report a successful process of using silicon overpressure, provided by silane in a CAD reactor during the anneal, to prevent the destruction of the silicon carbide surface, This process has proved to be robust and has resulted in ion activation at a annealing temperature of 1600$^{\circ}C$ without degradation of the crystal surface as determined by AFM and RBS. In addition XPS was used to look at the surface and near surface chemical states for annealing temperatures of up to 1700$^{\circ}C$. The surface and near surface regions to approximately 6 nm in depth was observed to contain no free silicon or other impurities thus indicating that the process developed results in an atomically clean SiC surface and near surface region within the detection limits of the instrument(${\pm}$1 at %).

• Journal of Sensor Science and Technology
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• v.2 no.1
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• pp.95-99
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• 1993

a-Si : H TFTs for image sensor have been fabricated and their operational characteristics have been investigated. Hydrogenated amorphous silicon nitride(a-SiN : H) films were used for the gate insulator and $n^{+}$-a-Si : H films were depostied for the source and drain contact. The thicknesses of a-SiN : H and a-Si : H films were $2000{\AA}$, respectively and the thickness of $n^{+}$-a-Si : H film was $500{\AA}$. Also the channel length and channel width of a-Si : H TFTs were $50{\mu}m$ and $1000{\mu}m$, respectively. The ON/OFF current ratio, threshold voltage, and field effect mobility of fabricated a-Si : H TFTs were $10^{5}$, 6.3 V, and $0.15cm^{2}/V{\cdot}s$, respectively.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.31 no.1
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• pp.6-10
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• 2018

Ni germanide (NiGe) is a promising alloy material with small contact resistance at the source/drain (S/D) of Ge MOSFETs. However, it is necessary to reduce the specific contact resistance between NiGe and the doped Ge S/D region in high-performance MOSFETs. In this study, a novel method is proposed to reduce the specific contact resistance between NiGe and p-type Ge (p-Ge) using a Tb interlayer. The specific contact resistance between NiGe and p-Ge was successfully decreased with the introduction of the Tb interlayer. To investigate the mechanism behind the reduction in the specific contact resistance, the elemental distribution and crystalline structure of NiGe were analyzed using secondary ion mass spectroscopy and X-ray diffraction. It is likely that the reduction in specific contact resistance was caused by an increase in the concentration of boron in the space between NiGe and p-Ge due to the influence of the Tb interlayer.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.467-468
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• 2006

We report on the fabrication of P3HT-based thin-film transistors (TFT) that consist of indium-zinc-oxide (IZO), PVP (poly-vinyl phenol), and Ni for the source-drain (S/D) electrode, gate dielectric, and gate electrode, respectively. The IZO S/D electrodes of which the work function is well matched to that of P3HT were deposited on a P3HT channel by thermal evaporation of IZO and showed a moderately low but still effective transmittance of ~25% in the visible range along with a good sheet resistance of ${\sim}60{\Omega}/{\square}$. The maximum saturation current of our P3HT-based TFT was about $15{\mu}A$ at a gate bias of -40V showing a high field effect mobility of $0.05cm^2/Vs$ in the dark, and the on/off current ratio of our TFT was about $5{\times}10^5$. It is concluded that jointly adopting IZO for the S/D electrode and PVP for gate dielectric realizes a high-quality P3HT-based TFT.