• Journal of Information Processing Systems
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• v.14 no.2
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• pp.499-509
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• 2018

Recently, hybrid transactional memory (HyTM) has gained much interest from researchers because it combines the advantages of hardware transactional memory (HTM) and software transactional memory (STM). To provide the concurrency control of transactions, the existing HyTM-based studies use a bloom filter. However, they fail to overcome the typical false positive errors of a bloom filter. Though the existing studies use a global lock, the efficiency of global lock-based memory allocation is significantly low in multi-core environment. In this paper, we propose an efficient hybrid transactional memory scheme using near-optimal retry computation and sophisticated memory management in order to efficiently process transactions in multi-core environment. First, we propose a near-optimal retry computation algorithm that provides an efficient HTM configuration using machine learning algorithms, according to the characteristic of a given workload. Second, we provide an efficient concurrency control for transactions in different environments by using a sophisticated bloom filter. Third, we propose a memory management scheme being optimized for the CPU cache line, in order to provide a fast transaction processing. Finally, it is shown from our performance evaluation that our HyTM scheme achieves up to 2.5 times better performance by using the Stanford transactional applications for multi-processing (STAMP) benchmarks than the state-of-the-art algorithms.

• KIISE Transactions on Computing Practices
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• v.23 no.8
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• pp.466-472
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• 2017

Hardware Transactional Memory (HTM) has greatly changed the parallel programming paradigm for transaction processing. Since Intel has recently proposed Transactional Synchronization Extension (TSX), a number of studies based on HTM have been conducted. However, the existing studies support conflict prediction for a single cause of the transaction processing and provide a standardized TSX environment for all workloads. To solve the problems, we propose an efficient hardware transactional memory scheme for processing transactions in multi-core in-memory environment. First, the proposed scheme determines whether to use Software Transactional Memory (STM) or the serial execution as a fallback path of HTM by using a prediction matrix to collect the information of previously executed transactions. Second, the proposed scheme performs efficient transaction processing according to the characteristic of a given workload by providing a retry policy based on machine learning algorithms. Finally, through the experimental performance evaluation using Stanford transactional applications for multi-processing (STAMP), the proposed scheme shows 10~20% better performance than the existing schemes.

• Proceedings of the Korean Society of Computer Information Conference
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• 2016.07a
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• pp.3-4
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• 2016

멀티스레드 프로그램의 수행 중에 발생할 수 있는 자료경합은 프로그래머가 의도하지 않은 비결정적 수행으로 인해 신뢰할 수 없는 프로그램의 결과를 발생시킨다. 이러한 자료경합의 디버깅을 위해서 시간 및 자원적 비용이 과도하게 발생하기 때문에 프로그램의 수행 중에 이를 용인하고 치유하는 것이 중요하다. 본 논문은 멀티스레드 프로그램을 대상으로 소프트웨어 트랜잭셔널 메모리(STM)를 사용하여 공유변수에 대한 트랜잭션 영역을 설정하고 공유변수에 대한 이벤트 충돌 유형에 따른 자료경합 치유기법을 설계한다. 최종적으로는 프로그램 수행 중에 자료경합을 치유하는 기법의 실현가능성을 확인한다.

• The Journal of Korean Institute of Next Generation Computing
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• v.13 no.2
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• pp.49-61
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• 2017

Transactional Memory (TM) has greatly changed the parallel programming paradigm for transaction processing and is classified into STM, HTM, HyTM according to hardware or software frameworks. However, the existing studies have a problem that they provide static retry policy for all workloads. To solve the problems, we propose an hybrid transactional memory scheme using sampling-based adaptive retry policy in multi-core environment. First, the proposed scheme determines whether to use STM or HTM according to the characteristic of a transaction. Otherwise, it executes HTM and STM concurrently by using a bloom filter. Second, the proposed scheme provides adaptive retry policy for HTM according to the characteristic of transactions in each workload. Finally, through the experimental performance evaluation using STAMP, the proposed scheme shows 10~20% better performance than the existing schemes.

• Journal of Software Assessment and Valuation
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• v.17 no.2
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• pp.19-29
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• 2021

Blockchain technology fulfills the reliance requirement and is now entering a new stage of performance. However, the current blockchain technology has significant disadvantages in scalability and latency because of its architecture. Therefore, to adopt blockchain technology to real industry, we must overcome the performance issue by redesigning blockchain architecture. This paper introduces several element technologies and a novel blockchain architecture TPAC, that preserves blockchain's technical advantage but shows more stable and faster transaction processing performance and low latency.

• Proceedings of the Korea Information Processing Society Conference
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• 2010.04a
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• pp.226-229
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• 2010

최근 프로세서가 코어 개수를 늘리는 구조로 발전함에 따라 병렬프로그래밍의 중요성이 더욱 강조되고 있다. 병렬프로그래밍에서 발생하는 공유자원에 대한 경쟁조건을 제어하기 위한 효율적인 방법으로 여러 가지 락-프리 동기화 기법이 제안되어 왔다. 그 중 소프트웨어 트랜잭션 메모리는 지금까지 하드웨어적인 방법과 소프트웨어적인 방법 등 여러 가지 방법으로 구현되었지만 여러 가지 하드웨어적인 제약과 기존의 소스코드를 수정해야 하는 문제점이 있다. 이러한 문제를 해결하기 위해 본 논문에서는 동적 코드 변환기술을 이용한 소프트웨어 트랜잭션 메모리 기법을 제안하고 기존 구현과 비교 평가하였다.