• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.25 no.2
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• pp.80-86
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• 2011

This paper presents an integrated variable amplitude high voltage pulse generation circuit with low power and small size for driving industrial piezoelectric printer heads. To solve the problems of large size and power overhead of conventional pulse generators that usually assembled with multiple high-cost discrete ICs on a PCB board, we have designed a new integrated circuit (IC) chip. Since all the functions are integrated on to a single-chip it can achieve low cost and control the high-voltage output pulse with variable amplitudes as well. It can also digitally control the rising and falling times of an output high voltage pulse by using programmable RC time control of the output buffer. The proposed circuit has been designed and simulatedd in a 180[nm] Bipolar-CMOS-DMOS (BCD) technology using HSPICE and Cadence Virtuoso Tools. The proposed single-chip pulse generation circuit is suitable for use in industrial printer heads requiring a variable high voltage driving capability.

• Journal of the Korean Ceramic Society
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• v.28 no.9
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• pp.675-682
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• 1991

Among many problems that need to be solved in the process of preparing multilayer chip LC filters, we studied the control of shrinkage in order to prevent the crack, warpage, and/or delamination which occurs at the interface between the inductance (L part) and the capacitance (C part). Shrinkage was controlled by compositions, powder size, calcining temperature and amount of organic binder. Capacitance sheet was prepared by mixing 65 wt% binder with the composition of 96 wt% TiO2 having an average particle size of 0.5 $\mu\textrm{m}$, 3 wt% CuO. After small amount of MnO2 and SiO2 added, it was calcined at 750$^{\circ}C$ for 2 hr. Inductance sheet was prepared by mixing 60 wt% binder with the composition of 49.5% mol% Fe2O3, 20.5 mol% ZnO, 20 mol% NiO and 10 mol% CuO which was calcined at 775$^{\circ}C$ for 2 hr. These sheets was laminated at 250 kg/$\textrm{cm}^2$, and cofired at 900$^{\circ}C$ for 2 hr to give rise to a multilayer chip LC filter without any warpage.

• Journal of Institute of Control, Robotics and Systems
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• v.22 no.7
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• pp.513-518
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• 2016

The piezoelectric actuating device is known for its large power density and simple structure. It can generate a larger force than a conventional actuator and has also wide bandwidth with fast response in a compact size. To control the piezoelectric actuator, we need an analog signal conditioning circuit as well as digital microcontrollers. Conventional microcontrollers are not equipped with an analog part and need digital-to-analog converters, which makes the system bulky compared with the small size of piezoelectric devices. To overcome these weaknesses, we are developing a single-chip controller that can handle analog and digital signals simultaneously using mixed-signal FPGA technology. This gives more flexibility than traditional fixed-function microcontrollers, and the control speed can be increased greatly due to the parallel processing characteristics of the FPGA. In this paper, we developed a floating-point multiplier, PWM generator, 80-kHz power control loop, and 1-kHz position feedback control loop using a single mixed-signal FPGA. It takes only 50 ns for single floating-point multiplication. The PWM generator gives two outputs to control the charging and discharging of the high-voltage output capacitor. Through experimentation and simulation, it is demonstrated that the designed control loops work properly in a real environment.

• Proceedings of the KIPE Conference
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• 2002.07a
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• pp.451-454
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• 2002

In this paper, studied on the one-chip design of low cost for the micro-stepping drive having 5-phase Pentagon Type winding. Micro-stepping method in order to eliminate effectively the resonant phenomena and to Increase the positional resolution. This paper proposed trapezoidal current wave- form for current control and provided design- method by using only one-chip of low cost. Therefore the drive will be simple and small size. Also the drive will have a lot of advantage at commercial business. Finally the above study has been implemented on the VHDL. Simulation has been performed to verify the PWM for micro-stepping drive.

• Journal of the Korean Society for Precision Engineering
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• v.9 no.4
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• pp.147-153
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• 1992

This study was undertaken to investigate the cutting behaviour of super duralumin (A2024-T3) with sintered carbide tool(P20). The cutting test was carried out under different conditions such as cutting speed, cutting depth and rake angle, etc. The specific cutting force Kc and Kt of vertical and radial forces decreases as cutting speed increases, especially the decrease rate of Kt becomes larger than of Kc as cutting speed increases. Kc and Kt in small cutting depth are much affected by work-hardening of surface layer. The chip width and shear angle become layer as cutting depth increases, especially chip width at feed of 0.1mm almost approaches cutting width. Relation between the friction coefficient of chip side and tool rake angle side can make the modelization studying the built-up edge size. The shear angle model equation of super duralumin generally agree with theory of Ernst-Merchant.

• International journal of advanced smart convergence
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• v.11 no.2
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• pp.53-58
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• 2022

In this paper, w-band frequency synthesizer was developed for frequency-modulated continuous wave (FMCW) radar sensors. To achieve a small size and high performance, We designed and manufactured w-band MMIC chips such as up-converter one-chip, multiplier, DA (Drive Amplifier) MMIC(Monolithic Microwave Integrated Circuit), etc. And interposer technology was applied between the W-band multiplier and the DA MMIC chip. As a result, the measured phase noise was -106.10 dBc@1MHz offset, and the frequency switching time of the frequency synthesizer was less than 0.1 usec. Compared with the w-band frequency synthesizer using purchased chips, the developed frequency synthesizer showed better performance.

• Journal of Biomedical Engineering Research
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• v.36 no.4
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• pp.86-94
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• 2015

In order for medical devices to be used outside hospital, they have to be not only of small size but also power consumption has to be kept at low level. This study investigates the feasibility of application of ADS1298 ECG single-chip solution developed by Texas Instruments Inc. for use in development of a new platform for diagnostic resting ECG. To prove the feasibility of commercial products based on the ADS1298 chip, the performance of the ADS1298 chip was measured in terms of input impedance, common mode rejection, frequency response, and input dynamic range using the testing method under the suitability criteria of the IEC 60601-2-25 standard. Result of the this study shows that commercialization of the ECG products based on the ADS1298 ECG single-chip solution that satisfies the international standards would be possible, if the manufactures take the filter characteristics into account in building a new platform for diagnostic resting ECG.

• Journal of IKEEE
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• v.11 no.4
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• pp.145-151
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• 2007

In this work, small-size, high-performance solenoid-type RF chip inductors utilizing a low-loss ${Al_2}{O_3}$ core material were investigated. The size of the chip inductors fabricated in this work were $0.86{\times}0.46{\times}0.45m^3$, $1.5{\times}1.0{\times}0.7m^3$, $2.1{\times}1.5{\times}1.0m^3$, and $2.4{\times}2.0{\times}1.4m^3$ and copper (Cu) wire with $27{\sim}40{\mu}m$ diameter was used as the coils. High frequency characteristics of the inductance, quality factor, and impedance of developed inductors were measured using an RF Impedance/Material Analyzer (HP4291B with HP16193A test fixture). It was observed that the developed inductors with the number of turns of 7 have the inductance of 13 to 100nH and exhibit the self-resonant frequency (SRF) of 6.4 to 1.1GHz. The SRF of inductors decreases with increasing the inductance and the inductors have the quality factor of 50 to 80 in the frequency range of 300MHz to 1.3GHz. In this study, small-size solenoid-type RF chip inductors with high inductance and high quality factor were fabricated successfully.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.108-116
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• 2013

The input buffer in Network on Chip (NoC) router plays a key role in on-chip-network performance, which is utilized in flow control and virtual channel. However, increase in area and power due to input buffers as the network size gets larger is becoming severe. To solve this problem, a bufferless deflection routing without input buffer was suggested. Since the bufferless deflection routing shows poor performance at high network load, other approaches which combine the deflection routing with small size side buffers were also proposed. Nonetheless these new methods still show deficiencies caused by frequent path collisions. In this paper, we propose a modified deflection routing technique using a location based priority. In comparison with existing deflection routers, experimental results show improvement by 12% in throughput with only 3% increase in area.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1066-1070
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• 2003

Recently technologies have created new principle and theory but the PID control system remains its popularity as the PID controller contains simple structure, including maintenance and parameter adjustment being so simple. Thus, this paper proposes auto tune PID by fuzzy logic controller based on FPGA which to achieve real time and small size circuit board. The digital PID controller design to consist of analog to digital converter which use chip TDA8763AM/3 (10 bit high-speed low power ADC), digital to analog converter which use two chip DAC08 (8 bit digital to analog converters) and fuzzy logic tune digital PID processor embedded on chip FPGA XC2S50-5tq-144. The digital PID processor was designed by fundamental PID equation which architectures including multiplier, adder, subtracter and some other logic gate. The fuzzy logic tune digital PID was designed by look up table (LUT) method which data storage into ROM refer from trial and error process. The digital PID processor verified behavior by the application program ModelSimXE. The result of simulation when input is units step and vary controller gain ($K_p$, $K_i$ and $K_d$) are similarity with theory of PID and maximum execution time is 150 ns/action at frequency are 30 MHz. The fuzzy logic tune digital PID controller based on FPGA was verified by control model of level control system which can control level into model are correctly and rapidly. Finally, this design use small size circuit board and very faster than computer and microcontroller.