• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.9
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• pp.971-978
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• 2010

In this paper, we propose a compact multiple meander RFID tag antenna with broadband characteristic. The proposed tag antenna has been designed using the multiple meander form to effectively minimize the U-shaped half wavelength dipole antenna as the radiator part. The commercial tag chip is attached to the upper center of the rectangular shaped feed for impedance matching. The size of the antenna is $20{\times}19.7\;mm^2$ and VSWR<5.8 bandwidth is 855~964 MHz which covers the world UHF RFID bandwidth.

• Journal of Sensor Science and Technology
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• v.14 no.3
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• pp.137-143
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• 2005

Research in the field of biosensor has enormously increased over the recent years. The metal-oxide semiconductor field effect transistor (MOSFET) type protein sensor offers a lot of potential advantages such as small size and weight, the possibility of automatic packaging at wafer level, on-chip integration of biosensor arrays, and the label-free molecular detection. We fabricated MOSFET protein sensor and proposed the gold-black electrode as the gate metal to improve the response. The experimental results showed that the output voltage of MOSFET protein sensor was varied by concentration of albumin proteins and the gold-black gate increased the response up to maximum 13 % because it has the larger surface area than that of planar-gold gate. It means that the expanded gate allows a larger number of ligands on same area, and makes the more albumin proteins adsorbed on gate receptor.

• Journal of Sensor Science and Technology
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• v.27 no.1
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• pp.31-35
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• 2018

This paper describes a low-power, SNDR (signal-to-noise and distortion ration) enhanced SAR (successive approximation register) type 12b ADC (analog-to-digital converter) with noise shaping technique. For low power consumption and small chip size of the DAC (digital-to-analog converter), the top plate sampling technique and the dummy capacitor switching technique are used to implement 12b operation with a 10b capacitor array in DAC. Noise shaping technique is applied to improve the SNDR by reducing the errors from the mismatching of DAC capacitor arrays, the errors caused by attenuation capacitor and the errors from the comparator noise. The proposed SAR ADC is designed with a $0.18{\mu}m$ CMOS process. The simulation results show that the SNDR of the SAR ADC without the noise shaping technique is 71 dB and that of the SAR ADC with the noise shaping technique is 84 dB. We can achieve the 13 dB improvement in SNDR with this noise shaping technique. The power consumption is $73.8{\mu}W$ and the FoM (figure-of-merit) is 5.2fJ/conversion-step.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.2 no.3
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• pp.359-365
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• 1998

The portable two way radio telephone amongst GMDSS equipment in the vessel is very important portable wireless one for search and rescue in distress situation. Although the portable two way radio telephone must be equipped with in the vessel by IMO & RR, other kinds of wireless tranceivers are widely used to communicate with crew members who are separately appointed at bridge forecastle and poop in leaving or arriving at the port, passing through a narrow canal or voyaging in the foggy weather, Most of those wireless tranceivers except portable two way radio telephone are allocated at 27MHz band with PTT simplex system that makes crew members difficult to work effectively in the vessel. In this research 900MHz band FDD(frequency duplex division) tranceiver system is studied to help crew members in the vessel to communicate with themselves freely and to work easily meanwhile with simple operation. 900MHz band FDD tranceiver system uses one chip FM frontend IC to realize the miniaturization and downsizing of tranceiver and small size head set attached to helmet. The credibility of this research's result is highly evaluated by circuit analysis with computer aided simulation, and partly modified 900MHz band cordless phone circuit.

• Journal of Sensor Science and Technology
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• v.22 no.5
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• pp.352-356
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• 2013

We developed a novel fabrication method of polydimethylsioxane (PDMS) lens, which can easily control the shapes of the lens using soft lithography with common photolithography and water droplet molding. A mold for PDMS lens was prepared by patterning of hydrophobic photoresist on the hydrophilic substrate and dispensing small water droplets onto the predefined hydrophilic patterns. The size of patterns determined the dimension of the lens and the dispensed volume of the water droplet decided the radius of curvature of the PDMS lens independently. The water droplet with photoresist pattern played a robustly fixed mold for lens due to difference in wettability. The radius of curvature could be calculated theoretically because the water droplets could approximate spherical cap on the substrate. Finally, concave and convex PDMS lenses which could reduce or magnify optically were fabricated by curing of PDMS on the prepared mold. The measured radii of the fabricated PDMS lenses were well matched with the estimated values. We believe that our simple and efficient fabrication method can be adopted to PDMS microlens and extended to micro optical device, lab on a chip, and sensor technology.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1998.05a
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• pp.365-370
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• 1998

The portable two way radio telephone amongst GMDSS equipment in the vessel is very important portable wireless one for search and rescue in distress situation. Although the portable two way radio telephone must be equipped with in the vessel by IMO RR, other kinds of wireless tranceivers are widely used to communicate with crew members who are separately appointed at bridge forecastle and poop in leaving or arriving at the port, passing through a narrow canal or voyaging in the foggy weather. Most of those wireless tranceivers except portable two way radio telephone are allocated at 27MHz band with PTT simplex system that makes crew members difficult to work effectively in the vessel. In this research 900MHz band FDD(frequency duplex division) tranceiver system is studied to help crew members in the vessel to communicate with themselves freely and to work easily meanwhile with simple operation. 900MHz band FDD tranceiver system uses one chip FM frontend IC to realize the miniaturization and downsizing of tranceiver and small size head set attached to helmet. The credibility of this research's result is highly evaluated by circuit analysis with computer aided simulation. and partly modified 900MHz band cordless phone circuit.

• Proceedings of the KSRS Conference
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• 2002.10a
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• pp.465-470
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• 2002

A novel phased array antenna system for space-borne polarimetric SAR is proposed and completed in this paper.The antenna system assures polarimetric and multi-mode capability of SAR. It has broadband, high polarization isolation and high port to port isolation. The antenna system is composed of broadband polarimetric microstrip antenna, T/R modules and multifunction beam controller nit. The polarimetric microstrip antenna has more than 100MHz bandwidth at L-band with -30dB polarization isolation and high port to port isolation. The microstrip element and T/R module's structure and characteristics, the subarray's performances measuring results are presented in detail in this paper. A design scheme on beam controller of the phased array antenna is also proposed and completed, which is based on Digital Signal Processing (DSP) chip -TMS320F206. This beam controller unit has small size and high reliability compared with general beam controller. In addition, the multifunction beam controller unit can acquire and then send the T/R module's working states to detection system in real time.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.55-64
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• 2006

This work proposes a calibration-free 14b 70MS/s 0.13um CMOS ADC for high-performance integrated systems such as WLAN and high-definition video systems simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs signal insensitive 3-D fully symmetric layout techniques in two MDACs for high matching accuracy without any calibration. A three-stage pipeline architecture minimizes power consumption and chip area at the target resolution and sampling rate. The input SHA with a controlled trans-conductance ratio of two amplifier stages simultaneously achieves high gain and high phase margin with gate-bootstrapped sampling switches for 14b input accuracy at the Nyquist frequency. A back-end sub-ranging flash ADC with open-loop offset cancellation and interpolation achieves 6b accuracy at 70MS/s. Low-noise current and voltage references are employed on chip with optional off-chip reference voltages. The prototype ADC implemented in a 0.13um CMOS is based on a 0.35um minimum channel length for 2.5V applications. The measured DNL and INL are within 0.65LSB and l.80LSB, respectively. The prototype ADC shows maximum SNDR and SFDR of 66dB and 81dB and a power consumption of 235mW at 70MS/s. The active die area is $3.3mm^2$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.7
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• pp.1332-1339
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• 2001

SoC(System on Chip) technology is widely used in the field of embedded systems by providing high flexibility for a specific application domain. An important aspect of development any new embedded system is verification which usually requires lengthy software and hardware co-design. To reduce development cost of design effort, the instruction set of microprocessor must be suitable for a high level language compiler. And FPGA prototype system could be derived and tested for design verification. In this paper, we propose a 16 bit FPGA microprocessor, which is tentatively-named EISC16, based on an EISC(Extendable Instruction Set Computer) architecture for embedded applications. The proposed EISC16 has a 16 bit fixed length instruction set which has the short length offset and small immediate operand. A 16 bit offset and immediate operand could be extended using by an extension register and an extension flag. We developed a cross C/C++ compiler and development software of the EISC16 by porting GNU on an IBM-PC and SUN workstation and compared the object code size created after compiling a C/C. standard library, concluding that EISC16 exhibits a higher code density than existing 16 microprocessors. The proposed EISC16 requires approximately 6,000 gates when designed and synthesized with RTL level VHDL at Xilinix's Virtex XCV300 FPGA. And we design a test board which consists of EISC16 ROM, RAM, LED/LCD panel, periodic timer, input key pad and RS-232C controller. 11 works normally at 7MHz Clock.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.4
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• pp.91-96
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• 2014

Through silicon via (TSV) technology is to form a via hole in a silicon chip, and to stack the chips vertically for three-dimensional (3D) electronics packaging technology. This can reduce current path, power consumption and response time. In this study, Cu-filling substrate size was changed from Si-chip to a 4" wafer to investigate the behavior of Cu filling in wafer level. The electrolyte for Cu filling consisted of $CuSO_4$ $5H_2O$, $H_2SO_4$ and small amount of additives. The anode was Pt, and cathode was changed from $0.5{\times}0.5cm^2$ to 4" wafer. As experimental results, in the case of $5{\times}5cm^2$ Si chip, suitable distance of electrodes was 4cm having 100% filling ratio. The distance of 0~0.5 cm from current supplying location showed 100% filling ratio, and distance of 4.5~5 cm showed 95%. It was confirmed good TSV filling was achieved by plating for 2.5 hrs.