• Title/Summary/Keyword: small size chip

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Computer-Aided Design of Miniaturized Multilayer Band Pass Chip Filter (CAD에 의한 초소형 적층형 대역 통과 칩 필터 설계)

  • 강종윤;최지원;심성훈;박용욱;윤석진;김현재
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.15 no.1
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    • pp.56-60
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    • 2002
  • A low-temperature cofired-ceramic (LTCC) multi-layer ceramic (MLC) band-pass filter (BPF) is presented, which has the benefits of low cost and small size. The BPF is designed for an IMT-2000 handset. The computer-aided design technology is also presented. The BPF with an attenuation pole at below the passband has been discussed and realized. The equivalent circuit of the BPF was established by transmission lines and lumped capacitors. The frequency characteristics of the LTCC-MLC BPF is well acceptable for IMT-2000 application.

Development of an Ambulatory Wearable System for Continuous Patient Monitoring (휴대용 심전도 모니터링 계측 시스템 개발에 관한 연구)

  • Park, Chan-Won;Jeon, Chan-Min
    • Proceedings of the KIEE Conference
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    • 2003.11c
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    • pp.920-923
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    • 2003
  • An wearable electrocardiogram (ECG) monitoring system is a widely used non-invasive diagnostic tool for ambulatory patient who may be at risk from latent life-threatening cardiac abnormalities. In this paper, we have a portable ECG monitoring system with conductive fiber which was characterized by the small-size and the low power consumption. The system consists of conductive fibers, one-chip microcontroller, ECG preprocessing circuit, and monitoring software to be able to record and analyze in PC. ECG preprocessing circuit is made of pre-amplifier with gain of 10, band-pass filter with bandwidth of 0.5-120Hz and 2.5V offset circuit for A/D conversion. ECG signals obtained by sensor are included with corrupted noises such as a baseline wandering, 60 Hz power noise and interference noise by body movement. For cancellation corrupted noises in signals obtained by conductive fiber, we used the wavelet decomposition of wavelet transforms in MATLAB toolbox.

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Advancements in Capacitive Touch System and Stylus Technologies

  • Ha-Min Lee;Seung-Hoon Ko
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.37 no.5
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    • pp.465-475
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    • 2024
  • Due to changes in the form factor of display panels and touch screen panels in various devices, capacitive touch systems have evolved to address various issues such as low power consumption, noise immunity, and small chip size. Furthermore, some devices have applications that use a stylus. Since the stylus operates similarly to a finger touch, it encounters similar issues. Recent research trends focus on addressing key issues such as noise, which is primarily caused by the self-capacitor formed between the display cathode and the touch screen panel. In this paper, Various research papers discussing methods to eliminate external noise will be reviewed. These advancements enhance noise immunity in touch systems, making it easier to use thinner and more flexible panels. These progress make touch technology more versatile and reliable in various applications.

Evaluation of a Self-Adaptive Voltage Control Scheme for Low-Power FPGAs

  • Ishihara, Shota;Xia, Zhengfan;Hariyama, Masanori;Kameyama, Michitaka
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.10 no.3
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    • pp.165-175
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    • 2010
  • This paper presents a fine-grain supply-voltage-control scheme for low-power FPGAs. The proposed supply-voltage-control scheme detects the critical path in real time with small overheads by exploiting features of asynchronous architectures. In an FPGA based on the proposed supply-voltage-control scheme, logic blocks on the sub-critical path are autonomously switched to a lower supply voltage to reduce the power consumption without system performance degradation. Moreover, in order to reduce the overheads of level shifters used at the power domain interface, a look-up-table without level shifters is employed. Because of the small overheads of the proposed supply-voltage-control scheme and the power domain interface, the granularity size of the power domain in the proposed FPGA is as fine as a single four-input logic block. The proposed FPGA is fabricated using the e-Shuttle 65 nm CMOS process. Correct operation of the proposed FPGA on the test chip is confirmed.

A Fully Programmable Shader Processor for Low Power Mobile Devices (저전력 모바일 장치를 위한 완전 프로그램 가능형 쉐이더 프로세서)

  • Jeong, Hyung-Ki;Lee, Joo-Sock;Park, Tae-Ryong;Lee, Kwang-Yeob
    • Journal of IKEEE
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    • v.13 no.2
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    • pp.253-259
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    • 2009
  • In this paper, we propose a novel architecture of a general graphics shader processor without a dedicated hardware. Recently, mobile devices require the high performance graphics processor as well as the small size, low power. The proposed shader processor is a GP-GPU(General-Purpose computing on Graphics Processing Units) to execute the whole OpenGL ES 2.0 graphics pipeline by using shader instructions. It does not require the separate dedicate H/W such as rasterization on this fully programmable capability. The fully programmable 3D graphics shader processor can reduce much of the graphics hardware. The chip size of the designed shader processor is reduced 60% less than the sizes of previous processors.

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A Fracture Mechanics Approach on Delamination and Package Crack in Electronic Packaging(l) -Delamination- (반도체패키지에서의 층간박리 및 패키지균열에 대한 파괴역학적 연구 (1) -층간박리-)

  • 박상선;반용운;엄윤용
    • Transactions of the Korean Society of Mechanical Engineers
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    • v.18 no.8
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    • pp.2139-2157
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    • 1994
  • In order to understand the delamination between leadframe and epoxy molding compound in an electronic packaging of surface mounting type, the stress intensity factor, T-stress and J-integral in fracture mechanics are obtained. The effects of geometry, material properties and molding process temperature on the delamination are investigated taking into account the temperature dependence of the material properties, which simulates as more realistic condition. As the crack length increases the J-integral increases, which suggest that the crack propagates if it starts growing from the small size. The effects of the material properties and molding process temperature on stress intensity factor, T-stress is and J-integral are less significant than the chip size for the practical cases considered here. The T-stress is negative in all eases, which is in agreement with observation that interfacial crack is not kinked until the crack approaches the edge of the leadframe.

Analysis of Process Parameters to Improve On-Chip Linewidth Variation

  • Jang, Yun-Kyeong;Lee, Doo-Youl;Lee, Sung-Woo;Lee, Eun-Mi;Choi, Soo-Han;Kang, Yool;Yeo, Gi-Sung;Woo, Sang-Gyun;Cho, Han-Ku;Park, Jong-Rak
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.4 no.2
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    • pp.100-105
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    • 2004
  • The influencing factors on the OPC (optical proximity correction) results are quantitatively analyzed using OPCed L/S patterns. ${\sigma}$ values of proximity variations are measured to be 9.3 nm and 15.2 nm for PR-A and PR-B, respectively. The effect of post exposure bake condition is assessed. 16.2 nm and 13.8 nm of variations are observed. Proximity variations of 11.6 nm and 15.2 nm are measured by changing the illumination condition. In order not to seriously deteriorate the OPC, these factors should be fixed after the OPC rules are extracted. Proximity variations of 11.4, 13.9, and 15.2 nm are observed for the mask mean-to-targets of 0, 2 and 4 nm, respectively. The decrease the OPC grid size from 1 nm to 0.5 nm enhances the correction resolution and the OCV is reduced from 14.6 nm to 11.4 nm. The enhancement amount of proximity variations are 9.2 nm corresponding to 39% improvement. The critical dimension (CD) uniformity improvement for adopting the small grid size is confirmed by measuring the CD uniformity on real SRAM pattern. CD uniformities are measured 9.9 nm and 8.7 nm for grid size of 1 nm and 0.5 nm, respectively. 22% improvement of the CD uniformity is achieved. The decrease of OPC grid size is shown to improve not only the proximity correction, but also the uniformity.

A Study on the Thermo-Mechanical Stress of MEMS Device Packages (마이크로 머신(MEMS) 소자 패키지의 열응력에 대한 연구)

  • Jeon, U-Seok;Baek, Gyeong-Uk
    • Korean Journal of Materials Research
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    • v.8 no.8
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    • pp.744-750
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    • 1998
  • Unlike common device, MEMS(micro-electro-mechanical system) device consists of very small mechanical structures which determine the performance of the device. Because of its small mechanical structure inside. MEMS device is very sensitive to thermal stress caused by CTE(coefficient of thermal expansion) mismatch between its components. Therefore, its characteristics are affected by material properties. process temperature. and dimensions of each layer such as chip, adhesive and substrate. In this study. we investigated the change of the thermal stress in the chip attached to a substrate. With computer-aided finite element method (FEM), the computer simulation of the thermal stress was conducted on variables such as bonding material, process temperature, bonding layer thickness and die size. The commercial simulation program, ABAQUS ver5.6, was used. Subsequently 3-layer test samples were fabricated, and their degree of bending were measured by 3-D coordinate measuring machine. The experimental results were in good agreement with the simulation results. This study shows that the bonding layer could be the source of stress or act as the buffer layer for stress according to its elastic modulus and CTE. Solder adhesive layer was the source of stress due to its high elastic modulus, therefore high compressive stress was developed in the chip. And the maximum tensile stress was developed in the adhesive layer. On the other hand, polymer adhesive layer with low elastic modulus acted as buffer layer, and resulted in lower compressive stress. The maximum tensile stress was developed in the substrate.

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The design and FPGA implementation of a general-purpose LDI controller for the portable small-medium sized TFT-LCD (중소형 TFT-LCD용 범용 LDI 제어기의 설계 및 FPGA 구현)

  • Lee, Si-Hyun
    • Journal of the Korea Society of Computer and Information
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    • v.12 no.4
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    • pp.249-256
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    • 2007
  • AIn this paper, a new desist of LDI controller IC for general purpose is proposed for driving the LDI(LCD Driver Interface) controller in $4{\sim}9$ inches sized portable small-medium TFT-LCD(Thin Film Transistor addressed -Liquid Crystal Display) panel module. The designed LDI controller was verified on the FPGA(Reld Programmable Gate Array) test board, and was made the interactive operation with the commercial TFT-LCD panel successfully. The purpose of design is that it is standardized the LDI controller's operation by one LDI controller for driving all TFT-LCD panel without classifying the panel vendor, and size. The main advantage for new general-purpose LDI controller is the usage for the desist of all panel's SoG(System on a Glass) module because of the design for the standard operation. And in the previous method, it used each LDI controller for every LCD vendor, and panel size, but because a new one can drive all portable small-medium sized panel, it results in reduction of LDI controller supply price, and manufacturing cost of AV(Audio Video) board and panel. In the near future, the development of SoG IC(Integrated Circuit) for manufacturing more excellent functional TFT-LCD panel module is necessary. As a result of this research, the TFT-LCD panel can make more small size, and light weight, and it results in an upturn of domestic company's share in the world market. With the suggested theory in this paper, it expects to be made use of a basic data for developing and manufacturing for the SoG chip of TFT-LCD panel module.

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Low-Complexity Handheld 3-D Scanner Using a Laser Pointer (단일 레이저 포인터를 이용한 저복잡도 휴대형 3D 스캐너)

  • Lee, Kyungme;Lee, Yeonkyung;Park, Doyoung;Yoo, Hoon
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.64 no.3
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    • pp.458-464
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    • 2015
  • This paper proposes a portable 3-D scanning technique using a laser pointer. 3-D scanning is a process that acquires surface information from an 3-D object. There have been many studies on 3-D scanning. The methods of 3-D scanning are summarized into some methods based on multiple cameras, line lasers, and light pattern recognition. However, those methods has major disadvantages of their high cost and big size for portable appliances such as smartphones and digital cameras. In this paper, a 3-D scanning system using a low-cost and small-sized laser pointer are introduced to solve the problems. To do so, we propose a 3-D localization technique for a laser point. The proposed method consists of two main parts; one is a fast recognition of input images to obtain 2-D information of a point laser and the other is calibration based on the least-squares technique to calculate the 3-D information overall. To verified our method, we carry out experiments. It is proved that the proposed method provides 3-D surface information although the system is constructed by extremely low-cost parts such a chip laser pointer, compared to existing methods. Also, the method can be implemented in small-size; thus, it is enough to use in mobile devices such as smartphones.