• Title/Summary/Keyword: small hardware

Search Result 560, Processing Time 0.025 seconds

Research on Classification of Sitting Posture with a IMU (하나의 IMU를 이용한 앉은 자세 분류 연구)

  • Kim, Yeon-Wook;Cho, Woo-Hyeong;Jeon, Yu-Yong;Lee, Sangmin
    • Journal of rehabilitation welfare engineering & assistive technology
    • /
    • v.11 no.3
    • /
    • pp.261-270
    • /
    • 2017
  • Bad sitting postures are known to cause for a variety of diseases or physical deformation. However, it is not easy to fit right sitting posture for long periods of time. Therefore, methods of distinguishing and inducing good sitting posture have been constantly proposed. Proposed methods were image processing, using pressure sensor attached to the chair, and using the IMU (Internal Measurement Unit). The method of using IMU has advantages of simple hardware configuration and free of various constraints in measurement. In this paper, we researched on distinguishing sitting postures with a small amount of data using just one IMU. Feature extraction method was used to find data which contribution is the least for classification. Machine learning algorithms were used to find the best position to classify and we found best machine learning algorithm. Used feature extraction method was PCA(Principal Component Analysis). Used Machine learning models were five : SVM(Support Vector Machine), KNN(K Nearest Neighbor), K-means (K-means Algorithm) GMM (Gaussian Mixture Model), and HMM (Hidden Marcov Model). As a result of research, back neck is suitable position for classification because classification rate of it was highest in every model. It was confirmed that Yaw data which is one of the IMU data has the smallest contribution to classification rate using PCA and there was no changes in classification rate after removal it. SVM, KNN are suitable for classification because their classification rate are higher than the others.

A Tag Flow-Driven Deployment Simulator for Developing RFID Applications (RFID 애플리케이션 개발을 위한 태그 흐름기반 배치 시뮬레이터)

  • Moon, Mi-Kyeong
    • The KIPS Transactions:PartD
    • /
    • v.17D no.2
    • /
    • pp.157-166
    • /
    • 2010
  • More recently, RFID (Radio Frequency Identification) systems have begun to find greater use in various industrial fields. The use of RFID system in these application domains has been promoted by efforts to develop the RFID tags which are low in cost, small in size, and high in performance. The RFID applications enable the real-time capture and update of RFID tag information, while simultaneously allowing business process change through real-time alerting and alarms. These be developed to monitor person or objects with RFID tags in a place and to provide visibility and traceability of the seamless flows of RFID tags. In this time, the RFID readers should be placed in diverse locations, the RFID flows between these readers can be tested based on various scenarios. However, due to the high cost of RFID readers, it may be difficult to prepare the similar environment equipped with RFID read/write devices. In this paper, we propose a simulator to allow RFID application testing without installing physical devices. It can model the RFID deployment environment, place various RFID readers and sensors on this model, and move the RFID tags through the business processes. This simulator can improve the software development productivity by accurately testing RFID middleware and applications. In addition, when data security cannot be ensured by any fault, it can decide where the problem is occurred between RFID hardware and middleware.

Two Design Techniques of Embedded Systems Based on Ad-Hoc Network for Wireless Image Observation (애드 혹 네트워크 기반의 무선 영상 관측용 임베디드 시스템의 두 가지 설계 기법들)

  • LEE, Yong Up;Song, Chang-Yeoung;Park, Jeong-Uk
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.39A no.5
    • /
    • pp.271-279
    • /
    • 2014
  • In this paper, the two design techniques of the embedded system which provides a wireless image observation with temporary ad-hoc network are proposed and developed. The first method is based on the embedded system design technique for a nearly real-time wireless short observation application, having a specific remote monitoring node with a built-in image processing function, and having the maximum rate of 1 fps (frame per second) wireless image transmission capability of a $160{\times}128$size image. The second technique uses the embedded system for a general wireless long observation application, consisting of the main node, the remote monitoring node, and the system controller with built-in image processing function, and the capability of the wireless image transmission rate of 1/3 fps. The proposed system uses the wireless ad-hoc network which is widely accepted as a short range, low power, and bidirectional digital communication, the hardware are consisted of the general developed modules, a small digital camera, and a PC, and the embedded software based upon the Zigbee stack and the user interface software are developed and tested on the implemented module. The wireless environment analysis and the performance results are presented.

Performance improvement on mobile devices using MVC+Prefetch Controller Pattern (MVC+Prefetch Controller 패턴을 사용한 모바일 기기의 성능향상 기법)

  • Im, Byung-Jai;Lee, Eun-Seok
    • The KIPS Transactions:PartD
    • /
    • v.18D no.3
    • /
    • pp.179-184
    • /
    • 2011
  • Current mobile devices have surpassed its boundaries as a more communication tool to a smart device which provides additional features. These features have supported the smart life of its users, but have reached its limit from low-performance processors and short-battery time. These issues can be resolved b implementing higher performing hardware, but they come with a burden of high cost. This paper introduces a new way of managing computing resources in a mobile device by enhancing the quality of human-computer interaction. The real-speed felt by users are mainly influenced by the time it takes form a user's input to the device to display the completed result on the screen. Since the size of the screen for mobile devices are small, if the processor only fetch data to be used for displaying on screen, the time can be significantly reduced. MVC+Prefetch Controller pattern accomplished this goal by using the minimum amount of data from DB to fetch display and still manages to support high-speed data transfer to achieve seamless display. This idea has been realized by practice using Samsung mobile phone S8500, which demonstrated the superior performance on user's perspective.

A Design and Implementation for a Reliable Data Storage in a Digital Tachograph (디지털 자동차운행기록계에서 안정적인 데이터 저장을 위한 설계 및 구현)

  • Baek, Sung Hoon;Son, Myunghee
    • KIPS Transactions on Computer and Communication Systems
    • /
    • v.1 no.2
    • /
    • pp.71-78
    • /
    • 2012
  • The digital tachograph is a device that automatically records speed and distance of a vehicle, together with the driver's activity and vehicle status at an accident. It records vehicle speed, break status, acceleration, engine RPM, longitude and latitude of GPS, accumulated distance, and so on. European Commission regulation made digital tachographs mandatory for all trucks from 2005. Republic of Korea made digital tachographs mandatory for all new business vehicles from 2011 and is widening the range of vehicles that must install digital tachographs year by year. This device is used to analyze driver's daily driving information and car accidents. Under a car accident that makes the device reliability unpredictable, it is very important to store driving information with maximum reliability for its original mission. We designed and implemented a practical digital tachograph. This paper presents a storage scheme that consists of a first storage device with small capacity at a high reliability and a second storage device with large capacity at a low cost in order to reliably records data with a hardware at a low cost. The first storage device records data in a SLC NAND flash memory in a log-structured style. We present a reverse partial scan that overcomes the slow scan time of log-structured storages at the boot stage. The scheme reduced the scan time of the first storage device by 1/50. In addition, our design includes a scheme that fast stores data at a moment of accident by 1/20 of data transfer time of a normal method.

An Importance Analysis of Coworking Space Organization and Operating Components (코워킹 스페이스의 구성과 운영요소에 대한 중요도 분석)

  • Bae, Chul Hee;Kim, Jung Youp;Lee, Hyun Seok
    • Korea Real Estate Review
    • /
    • v.28 no.4
    • /
    • pp.23-35
    • /
    • 2018
  • The shared-office business started with the lending of office spaces such as meeting rooms. From this came the coworking space, which maximizes the collaboration among the residents and promotes synergy among them. The purpose of this study was to analyze the characteristics of the coworking space. In addition, this study derived the factors that are considered important among the hardware- and software-level operating components, and presented the priorities according to the importance through a questionnaire survey and analysis for the employees currently utilizing a coworking space. For the results of the analysis, the top elements in the survey were found to be "spatial composition," "membership management," coworking management," and "architectural elements." In addition, when the general items were analyzed according to their characteristics, it was found that there was a difference in priority level among the elements of each characteristic. These results are expected to be useful when designing coworking spaces in the future. The results of this study can be used as the basic data for solving the problems of small companies and the environment, among others. Furthermore, the results of this study can be utilized as the basic data for the development of a collective shared community through linking at the local or national level, rather than being limited to a single space.

$AB^2$ Semi-systolic Architecture over GF$GF(2^m)$ ($GF(2^m)$상에서 $AB^2$ 연산을 위한 세미시스톨릭 구조)

  • 이형목;전준철;유기영;김현성
    • Journal of the Korea Institute of Information Security & Cryptology
    • /
    • v.12 no.2
    • /
    • pp.45-52
    • /
    • 2002
  • In this contributions, we propose a new MSB(most significant bit) algorithm based on AOP(All One Polynomial) and two parallel semi-systolic architectures to computes $AB^2$over finite field $GF(2^m)$. The proposed architectures are based on standard basis and use the property of irreducible AOP(All One Polynomial) which is all coefficients of 1. The proposed parallel semi-systolic architecture(PSM) has the critical path of $D_{AND2^+}D_{XOR2}$ per cell and the latency of m+1. The modified parallel semi-systolic architecture(WPSM) has the critical path of $D_{XOR2}$ per cell and has the same latency with PSM. The proposed two architectures, PSM and MPSM, have a low latency and a small hardware complexity compared to the previous architectures. They can be used as a basic architecture for exponentiation, division, and inversion. Since the proposed architectures have regularity, modularity and concurrency, they are suitable for VLSI implementation. They can be used as a basic architecture for algorithms, such as the Diffie-Hellman key exchange scheme, the Digital Signature Algorithm(DSA), and the ElGamal encryption scheme which are needed exponentiation operation. The application of the algorithms can be used cryptosystem implementation based on elliptic curve.

Implementation of RSA modular exponentiator using Division Chain (나눗셈 체인을 이용한 RSA 모듈로 멱승기의 구현)

  • 김성두;정용진
    • Journal of the Korea Institute of Information Security & Cryptology
    • /
    • v.12 no.2
    • /
    • pp.21-34
    • /
    • 2002
  • In this paper we propos a new hardware architecture of modular exponentiation using a division chain method which has been proposed in (2). Modular exponentiation using the division chain is performed by receding an exponent E as a mixed form of multiplication and addition with divisors d=2 or $d=2^I +1$ and respective remainders r. This calculates the modular exponentiation in about $1.4log_2$E multiplications on average which is much less iterations than $2log_2$E of conventional Binary Method. We designed a linear systolic array multiplier with pipelining and used a horizontal projection on its data dependence graph. So, for k-bit key, two k-bit data frames can be inputted simultaneously and two modular multipliers, each consisting of k/2+3 PE(Processing Element)s, can operate in parallel to accomplish 100% throughput. We propose a new encoding scheme to represent divisors and remainders of the division chain to keep regularity of the data path. When it is synthesized to ASIC using Samsung 0.5 um CMOS standard cell library, the critical path delay is 4.24ns, and resulting performance is estimated to be abort 140 Kbps for a 1024-bit data frame at 200Mhz clock In decryption process, the speed can be enhanced to 560kbps by using CRT(Chinese Remainder Theorem). Futhermore, to satisfy real time requirements we can choose small public exponent E, such as 3,17 or $2^{16} +1$, in encryption and verification process. in which case the performance can reach 7.3Mbps.

Design and Implementation of BNN-based Gait Pattern Analysis System Using IMU Sensor (관성 측정 센서를 활용한 이진 신경망 기반 걸음걸이 패턴 분석 시스템 설계 및 구현)

  • Na, Jinho;Ji, Gisan;Jung, Yunho
    • Journal of Advanced Navigation Technology
    • /
    • v.26 no.5
    • /
    • pp.365-372
    • /
    • 2022
  • Compared to sensors mainly used in human activity recognition (HAR) systems, inertial measurement unit (IMU) sensors are small and light, so can achieve lightweight system at low cost. Therefore, in this paper, we propose a binary neural network (BNN) based gait pattern analysis system using IMU sensor, and present the design and implementation results of an FPGA-based accelerator for computational acceleration. Six signals for gait are measured through IMU sensor, and a spectrogram is extracted using a short-time Fourier transform. In order to have a lightweight system with high accuracy, a BNN-based structure was used for gait pattern classification. It is designed as a hardware accelerator structure using FPGA for computation acceleration of binary neural network. The proposed gait pattern analysis system was implemented using 24,158 logics, 14,669 registers, and 13.687 KB of block memory, and it was confirmed that the operation was completed within 1.5 ms at the maximum operating frequency of 62.35 MHz and real-time operation was possible.

Effective 3-D GPR Survey for the Exploration of Old Remains (유적지 발굴을 위한 효율적 3차원 GPR 탐사)

  • Kim, Jung-Ho;Yi, Myeong-Jong;Son, Jeong-Sul;Cho, Seong-Jun;Park, Sam-Gyu
    • Geophysics and Geophysical Exploration
    • /
    • v.8 no.4
    • /
    • pp.262-269
    • /
    • 2005
  • Since the buried cultural relics are three-dimensional (3-D) objects in nature, 3-D survey is more preferable in archeological exploration. 3-D Ground Penetrating Radar (GPR) survey based on very dense data in principle, however, might need much higher cost and longer time of exploration than other geophysical methods commonly used for the archeological exploration, such as magnetic and electromagnetic methods. We developed a small-scale continuous data acquisition system which consists of two sets of GPR antennas and the precise positioning device tracking the moving-path of GPR antenna automatically and continuously. Since the high cost of field work may be partly attributed to establishing many profile lines, we adopted a concept of data acquisition at arbitrary locations not along the pre-established profile lines. Besides this hardware system, we also developed several software packages in order to effectively process and visualize the 3-D data obtained by the developed system and the data acquisition concept. Using the developed system, we performed 3-D GPR survey to investigate the possible historical remains of Baekje Kingdom at Buyeo city, South Korea, prior to the excavation. Owing to the newly devised system, we could obtain 3-D GPR data of this survey area having areal extent over about $17,000m^2$ within only six-hours field work. Although the GPR data were obtained at random locations not along the pre-established profile lines, we could obtain high-resolution 3-D images showing many distinctive anomalies, which could be interpreted as old agricultural lands, waterways, and artificial structures or remains. This cast: history led us to the conclusion that 3-D GPR method is very useful not only to examine a small anomalous area but also to investigate the wider region of the archeological interests.