• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.2
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• pp.141-146
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• 2017

In this paper, a gradient magnitude hardware architecture based on hardware folding design method is proposed for low power image feature extraction. For the hardware complexity reduction, the projection vector chracteristic of gradient magnitude is applied. The proposed hardware architecture can be implemented with the small degradation of the gradient magnitude data quality. The FPGA implementation result shows the 41% of logic elements and 62% embedded multiplier savings compared with previous work using Altera Cyclone VI (EP4CE115F29C7N) FPGA and Quartus II v16.0 environment.

• Journal of Industrial Technology
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• v.29 no.B
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• pp.127-131
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• 2009

This paper presents the development of smart counting system that is proper for grains with uneven unit weight or shape. This device can detect the small differences of a light beam and count the pulse from wave shape control, when the grain is going on the light screen, which is made by the light beam screen sensor. It can, different from the former conventional device, distinct the uneven grains for counting detect, by using the dedicated hardware and the software algorithm of the light sensor.

• Proceedings of the KIPE Conference
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• 1998.10a
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• pp.642-647
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• 1998

A new small-signal model for the controlled on-time boost power factor correction (PFC) circuit is presented. The proposed small-signal model is valid up to high frequencies over lKHz. The model can be used in designing the voltage feedback compensation of PFC circuits, the control bandwidth of which is maximized with auxiliary means of removing the low-frequency ripple from the output. The accuracy of the model is confirmed by a 200W experimental hardware

• Journal of Industrial Technology
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• v.27 no.B
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• pp.103-107
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• 2007

In this paper, the light screen sensing system is introduced and testified to detect small grains such as seeds or electronic chips of uneven sized. Two modules composed of transmitter-receiver sensor array and microprocessor-based sensor signal processing system are developed to realize the proposed system. Experimental results showed that the sensing signal was relatively clear and its counting performance was very stable.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.12
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• pp.93-101
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• 2007

Small area and low power implementation are important requirements for various multimedia processing hardware, especially for mobile environment. This paper presents a hardware architecture of H.264/AVC Intra Prediction module aiming on small area and low power. A single arithmetic unit was shared and processed sequentially for all mode decisions and computations to predict an image frame. As a result, we could get smaller area and smaller memory size compared to other existing implementations. The proposed architecture was verified using the Altera Excalibur device, and the implemented hardware has been described in Verilog-HDL and synthesized on Samsung STD130 0.18um CMOS Standard Cell Library using Synopsys Design Compiler. The synthesis result was about 11.9K logic gates and 1078 byte internal SRAM and the maximum operating frequency was 107Mhz. It consumes 879,617 clocks to process one QCIF frame, which means it can process 121.5 QCIF$(176\times144)$ frames per second, therefore it shows that it can be used for real time H.264/AVC encoding of various multimedia applications.

• Journal of the Korea Institute of Building Construction
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• v.13 no.4
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• pp.341-350
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• 2013

For this study, a series of interviews with engineers in the Korean construction industry was carried out through a formal workshop format to analyze the causes of the inferior quality of builders' hardware. The authors established the causes of defects in window hardware construction in relation to the three aspects of system, design, and construction as involving the following seven factors: lack of system (including low ability to create construction specifications); low social awareness of the importance of window hardware; low technical capability to create design drawings; low design costs; small manufacturing capacity; low construction cost; and short duration of construction. Among the seven causes, the biggest cause of defects in window hardware construction is the lack of a system (low ability to create construction specifications), followed by low technical capability to create design drawings. In addition, this study carried out basic research to create measures to prevent defects in window hardware construction by analyzing how such causes of defects are distributed depending on the scale of architectural firms and construction companies during actual projects.

• Journal of the Korea Institute of Military Science and Technology
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• v.16 no.2
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• pp.130-137
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• 2013

In this paper, decoupled controller design for Autonomous Underwater Vehicle(AUV) and its simulated performance test results and Hardware In the Loop Simulation(HILS) results are presented. Control system design is done using the PD control scheme. Stability analysis and step response of closed loop system under uncertain parameter condition are also presented. The results of full coupled nonlinear model simulation show the well applicability of the designed controller. From the results of HILS, we can verify performance of real time processing and implemented hardware for AUV.

• ETRI Journal
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• v.39 no.4
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• pp.525-534
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• 2017

A hardware-acceleration architecture that separates virtual network functions (VNFs) and network control (called HSN) is proposed to solve the mismatch between the simple flow steering requirements and strong packet processing abilities of software-defined networking (SDN) forwarding elements (FEs) in SDN/network function virtualization (NFV) architecture, while improving the efficiency of NFV infrastructure and the performance of network-intensive functions. HSN makes full use of FEs and accelerates VNFs through two mechanisms: (1) separation of traffic steering and packet processing in the FEs; (2) separation of SDN and NFV control in the FEs. Our HSN prototype, built on NetFPGA-10G, demonstrates that the processing performance can be greatly improved with only a small modification of the traditional SDN/NFV architecture.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.6
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• pp.1139-1143
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• 2007

For the possible application of monitoring or diagnosing heart sounds in an ubiquitous healthcare environment. a small and light electro-stethoscope that can be attached in human body should be exploited. With this aim, this study proposes a new style of electro-stethoscope device that is composed of four hardware modules in wearable style. For this ambulatory heart sound collecting device, the several tests must be performed to check portability and material capability for collecting heart sounds. It turned out to be that the multi-channel electro-stethoscope can detect heart sound signals well even if it is not pinpointed in the accurate stethoscope point on a heart. Consequently, our ambulatory electro-stethoscope hardware system can be applied to monitor or diagnose abnormal heart sounds in the ubiquitous healthcare system.

• Speech Sciences
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• v.11 no.3
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• pp.143-156
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• 2004

In this paper, we implemented a vocabulary-independent speech recognizer using the TMS320VC33 DSP. For this implementation, we had developed very small-sized recognition engine based on diphone sub-word unit, which is especially suited for embedded applications where the system resources are severely limited. The recognition accuracy of the developed recognizer with 1 mixture per state and 4 states per diphone is 94.5% when tested on frequently-used 2000 words set. The design of the hardware was focused on minimal use of parts, which results in reduced material cost. The finally developed hardware only includes a DSP, 512 Kword flash ROM and a voice codec. In porting the recognition engine to the DSP, we introduced several methods of using data and program memory efficiently and developed the versatile software protocol for host interface. Finally, we also made an evaluation board for testing the developed hardware recognition module.