• ETRI Journal
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• v.27 no.3
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• pp.312-318
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• 2005

Mid-span spectral inversion (MSSI) has to utilize high optical pump power, for its operation principle is based on a nonlinear optical wavelength conversion. In this paper, a low pump-power operation of MSSI-based chromatic dispersion compensation (CDC) has been achieved successfully, for the first time to our knowledge, by introducing a noise pre-reduction scheme in cascaded wavelength conversions with periodically poled $LiNbO_3$ waveguides at a relatively low operation temperature. As preliminary studies, phase-matching properties and operation-temperature dependence of the wavelength converter (WC) were characterized. The WC pumped at 1549 nm exhibited a wide conversion bandwidth of 59 nm covering the entire C-band and a conversion efficiency of -23.6 dB at 11 dBm pump power. CDC experiments were implemented with 2.5 and 10 Gb/s transmission systems over 100 km single-mode fiber. Although it is well-known that the signal distortion due to chromatic dispersion is not critical at a 2.5 Gb/s transmission, the clear recovery of eye patterns was identified. At 10 Gb/s transmission experiments, eye patterns were retrieved distinctly from seriously distorted ones, and notable improvements in bit-error rates were acquired at a low pump power of 14 dBm.

• Journal of Power Electronics
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• v.14 no.4
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• pp.733-741
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• 2014

The integration of photovoltaic (PV) energy sources into DC grid has gained considerable attention because of its enhanced conversion efficiency with reduced number of power conversion stages. During the integration process, a local control unit is normally included with every power conversion stage of the PV source to accomplish the process of maximum power point tracking. A centralized monitoring and supervisory control unit is required for monitoring, power management, and protection of the entire system. Therefore, we propose a field-programmable gate array (FPGA) based centralized control unit that integrates all local controllers with the centralized monitoring unit. The main focus of this study is on the process of integrating many local control units into a single central unit. In this paper, we present design and optimization procedures for the hardware implementation of FPGA architecture. Furthermore, we propose a transient analysis and control design methodology with consideration of the nonlinear characteristics of the PV source. Hardware experiment results verify the efficiency of the central control unit and controller design.

• Journal of Advanced Navigation Technology
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• v.10 no.2
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• pp.138-144
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• 2006

In this paper, dual mode FET mixer for WiBro and wireless LAN(WLAN) applications has been designed in the form of dual gate FET mixer by using the cascode structure of two single gate pHEMTs. The designed dual gate mixer has been optimized to have variable conversion gain for WiBro and WLAN applications in order to save dc power consumption. The LO to RF isolation of the designed mixer is more than 20dB from 2.3GHz to 2.5GHz band. With the LO power of 0dBm and RF power of -50dBm, the mixer shows 15dB conversion gain. When RF power increases from -50dBm to -20dBm, the conversion gain decreases to -2dB from 15dB with bias change. The variable conversion gain has several advantages. It can reduce the high dynamic range requirement of AGC burden at IF stage. Also, it can save the dc power dissipation of mixer up to 90%.

• International Journal of Internet, Broadcasting and Communication
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• v.15 no.3
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• pp.122-128
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• 2023

This paper proposes two kinds of single-balanced direct conversion quadrature receivers using selfoscillating LMVs in which the voltage-controlled oscillator (VCO) itself operates as a mixer while generating an oscillation. The two LMVs are complementary coupled and series coupled to generate the quadrature oscillating signals, respectively. Using a 65 nm CMOS technology, the proposed quadrature receivers are designed and simulated. Oscillating at around 2.4 GHz frequency, the complementary coupled quadrature receiver achieves the phase noise of -28 dBc/Hz at 1KHz offset and -109 dBc/Hz at 1 MHz offset frequency. The other series coupled receiver achieves the phase noise of -31 dBc/Hz at 1KHz offset and -109 dBc/Hz at 1 MHz offset frequency. The simulated voltage conversion gain of the two single-balanced receivers is 37 dB and 45 dB, respectively. The double-sideband noise figure of the two receivers is 5.3 dB at 1 MHz offset. The quadrature receivers consume about 440 μW dc power from a 1.0-V supply.

• KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
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• v.4B no.2
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• pp.65-72
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• 2004

Switching power supply systems are widely used in many industrial fields. Power factor correction (PFC) circuits have a tendency to be applied in new power supply designs. The input active power factor correction (APFC) circuits can be implemented in either the two-stage approach or the single-stage approach. The two-stage approach can be classified into boost type PFC circuit and dc/dc converter. The power factor correction circuit with a boost converter used as an input power source is studied in this paper. In a boost power factor correction circuit there are two feedback control loops, which are a current feedback loop and a voltage feedback loop. In this paper, the regulation performance of output voltage and compensator to improve the transient response presented at the continuous conduction mode (CCM) of the boost PFC circuit is analyzed. The validity of designed boost PFC circuit is confirmed by MATLAB simulation and experimental results.

• KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
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• v.11B no.3
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• pp.104-111
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• 2001

The design procedures and experimental results of a single-stage electronic ballast using half-bridge resonant inverter are presented in this paper. The proposed topology is based on a single-stage ballast which combines a boost converter and a half-bradge series resonant inverter. High power factor is achieved by using the boost semi-stage operating in discontinuous conduction mode and inverter semi-stage operated above resonant frequency to provide zero voltage switching is empolyed to ballast the fluorescent lamp Experimental results from the ballast system with 36W fluorescent

• KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
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• v.2B no.4
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• pp.207-213
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• 2002

The paper introduces a switched reluctance motor drive system based on an 80C31 and an Intel 80C 196KB single-chip microprocessor control. Advance schemes are used in turn-on and turn-off angles with the power converter's main switches during traction and regenerative braking. The principles of traction speed control and braking torque control are given. The hardware and software patterns in the 80c31 and the Intel 80C196KB single-chip microprocessor control system are also presented.

• Journal of Power Electronics
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• v.17 no.6
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• pp.1433-1444
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• 2017

A family of non-isolated DC-DC three-port converters (TPCs) that allows for a more flexible power flow among a renewable energy source, an energy storage device and a current-reversible DC bus is introduced. Most of the reported non-isolated topologies in this area consider only a power consuming load. However, for applications such as hybrid-electric vehicle braking systems and DC microgrids, the load power generating capability should also be considered. The proposed three-port family consists of one unidirectional port and two bi-directional ports. Hence, they are well-suited for photovoltaic (PV)-battery-DC bus systems from the power flow viewpoint. Three-port converters are derived by combining different commonly known power converters in an integrated manner while considering the voltage polarity, voltage levels among the ports and the overall voltage conversion ratio. The derived converter topologies are able to allow for seven different modes of operation among the sources and load. A three-port converter which integrates a boost converter with a buck converter is used as a design example. Extensions of these topologies by combining the soft-switching technique with the proposed design example are also presented. Experiment results are given to verify the proposed three-port converter family and its analysis.

• Proceedings of the KIPE Conference
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• 2000.07a
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• pp.636-640
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• 2000

A novel integrated battery charger/discharger converter for a standardized battery module is proposed. Instead of using separate charger and discharger converters. it integrates these two converters into a single converter in order to minimize the size. the integrated charger/discharger converter not only regulates the solar array output power including the peak power tracking capability but also controls the battery charging/discharging current depending on the solar array output power and the load power. In addition it offers a regulated bus voltage which simplifies the power distribution/conversion for the pay load.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.451-462
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• 2016

Photovoltaic energy conversion becomes main focus of many researches due to its promising potential as source for future electricity and has many advantages than the other alternative energy sources like wind, solar, ocean, biomass, geothermal etc. In Photovoltaic power generation multilevel inverters play a vital role in power conversion. The three different topologies, diode-clamped (neutral-point clamped) inverter, capacitor-clamped (flying capacitor) inverter and cascaded h-bridge multilevel inverter are widely used in these multilevel inverters. Among the three topologies, cascaded h-bridge multilevel inverter is more suitable for photovoltaic applications since each pv array can act as a separate dc source for each h-bridge module. This paper presents a single phase Cascaded H-bridge five level inverter for grid-connected photovoltaic application using sinusoidal pulse width modulation technique. This inverter output voltage waveform reduces the harmonics in the generated current and the filtering effort at the input. The control strategy allows the independent control of each dc-link voltages and tracks the maximum power point of PV strings. This topology can inject to the grid sinusoidal input currents with unity power factor and achieves low harmonic distortion. A PID control algorithm is implemented in Arm Processor LPC2148. The validity of the proposed inverter is verified through simulation and is implemented in a single phase 100W prototype. The results of hardware are compared with simulation results. The proposed system offers improved performance over conventional three level inverter in terms of THD.