• Proceedings of the KIEE Conference
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• 2009.04b
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• pp.118-120
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• 2009

본 논문에서는 직접 전력변환방식의 단상 sag/swell 보상기를 구현하였다. 제안된 보상기는 정현파 입력/ 출력 필터, 직렬연결 변압기와 dc 링크 커패시터부가 없는 단상 back-to-back PWM컨버터로 구성되어 있다. 이 보상기의 장점은 dc-link 진해 커패시터가 제거되어 전력회로부가 간단하게 구현되어 향상된 신뢰성 및 내구성을 확인 할 수 있으며 동시에 단상 전압 sag/swell을 보상하며 스위칭 손실을 줄이는 간단한 PWM 방법을 들 수 있다. 더구나, 제안된 방법은 일반적인 직접 전력변환방식에서 요구되어지는 복잡한 4-step 전류 방법이 필요 없는 간단한 전류제어방법을 채용할 수 있는 구조이며 제안된 보상기의 구조와 PWM 방법의 타당성을 프로토타입 하드웨어를 제작하여 실험결과로 보상기의 우수성을 확인하였다.

• Proceedings of the KIEE Conference
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• 2005.10c
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• pp.169-171
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• 2005

In this paper, a novel type of auxiliary switched capacitor assisted edge resonant soft switching PWM series load resonant high frequency inverter with two auxiliary edge resonant lossless inductor snubbers is proposed for small consumer induction heating appliances. The operation principle of this high frequency inverter is described using the switching mode equivalent circuits. The practical effectiveness of the newly proposed soft switching inverter are discussed as compared with the conventional soft switching high frequency inverters based on simulation and experimental results from an application point of view.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.535-536
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• 2005

Organic photovoltaic effects were studied in a device structure of ITO/CuPc/Al and ITO/CuPc/$C_{60}$/BCP/Al. A thickness of CuPc layer was varied from 10 nm to 50 nm, we have obtained that the optimum CuPc layer thickness is around 40 nm from the analysis of the current density-voltage characteristics in CuPc single layer photovoltaic cell. From the thickness-dependent photovoltaic effects in CuPc/$C_{60}$ heterojunction devices, higher power conversion efficiency was obtained in ITO/20nm CuPc/40nm $C_{60}$/Al, which has a thickness ratio (CuPc:$C_{60}$) of 1:2 rather than 1:1 or 1:3. Light intensity on the device was measured by calibrated Si-photodiode and radiometer/photometer of International Light Inc(IL14004).

• Journal of the Korean Physical Society
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• v.73 no.11
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• pp.1787-1793
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• 2018

The power conversion efficiency of perovskite solar cells has reached 23.3%. Although significant developments have been made through intensive studies, the stability issue is still challenging. Passivation of perovskite solar cells with a transparent polymer provides better stability; however, there are a few disadvantages of organic polymer such as low thermal stability, weak adhesion and the lack of water retention ability. In this work, we prepared a dual Parylene-F/C layer with 3-methacryloxypropyltrimethoxysilane, A-174, to combine the advantages of organic and inorganic materials. As a result, A-174 treated dual Parylene-F/C layer demonstrated improved passivation effects compared to a single Parylene layer due to the strong binding of Parylene and the water retention ability by $SiO_2$ formed from A-174. This synergetic effects can be expanded to the combination of other organic materials and organosilane compounds.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.3
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• pp.189-193
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• 2015

This paper provides the design techniques of a successive approximation register (SAR) type 12b analog-to-digital converter (ADC) for distributed maximum power point tracking (DMPPT) control in a photovoltaic system. Both a top-plate sampling technique and a $V_{CM}$-based switching technique are applied to the 12b capacitor digital-to-analog converter (CDAC). With these techniques, we can implement a 12b SAR ADC with a 10b capacitor array digital-to-analog converter (DAC). To enhance the accuracy of the ADC, a single-to-differential converted DAC is exploited with the dual sampling technique during top-plate sampling. Simulation results show that the proposed ADC can achieve a signal-to-noise plus distortion ratio (SNDR) of 70.8dB, a spurious free dynamic range (SFDR) of 83.3dB and an effective number of bits (ENOB) of 11.5b with bipolar CMOS LDMOD (BCDMOS) $0.35{\mu}m$ technology. Total power consumption is 115uW under a supply voltage of 3.3V at a sampling frequency of 1.25MHz. And the figure of merit (FoM) is 32.68fJ/conversion-step.

• Journal of the Optical Society of Korea
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• v.11 no.4
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• pp.192-195
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• 2007

A high-conversion efficiency, nanosecond pulsed optical parametric generation and amplification with repetition rate of 20 kHz based on a periodically poled MgO-doped stoichiometric lithium tantalate was presented. Pumped by a Q-switched $Nd:YVO_4$ laser at 1064 nm with a pumping power of 4.8W, the generated output power was 1.6W for the signal and idler waves, achieving a slope efficiency of 50%. Using a seed source at signal wave the amplified signal output-pulse energy reached $65{\mu}J$. The obtained maximum gain was 72.4 dB.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.1-9
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• 2012

A 10-b 500 MS/s A/D converter (ADC) with a hybrid calibration and error correction logic is described. The ADC employs a single-channel cascaded folding-interpolating architecture whose folding rate (FR) is 25 and interpolation rate (IR) is 8. To overcome the disadvantage of an offset error, we propose a hybrid self-calibration circuit at the open-loop amplifier. Further, a novel prevision digital error correction logic (DCL) for the folding ADC is also proposed. The ADC prototype using a 130 nm 1P6M CMOS has a DNL of ${\pm}0.8$ LSB and an INL of ${\pm}1.0$ LSB. The measured SNDR is 52.34-dB and SFDR is 62.04-dBc when the input frequency is 78.15 MHz at 500 MS/s conversion rate. The SNDR of the ADC is 7-dB higher than the same circuit without the proposed calibration. The effective chip area is $1.55mm^2$, and the power dissipates 300 mW including peripheral circuits, at a 1.2/1.5 V power supply.

• Journal of the Microelectronics and Packaging Society
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• v.6 no.3
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• pp.1-7
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• 1999

A single RF transceiver evaluation board have been developed for the purpose of application to the 900MHz band transceiver contained RF-IC chip And environment test was evaluated. The RF-IC chipset includes LNA(Low Noise Amplifier), down-conversion mixer, AGC(Automatic Gain Controller), switched capacitor filter and down sampling mixer. The RF evaluation board for the testing of chipset contained various external matching circuits, filters such as RF/IF SAW(Surface Acoustic Wave) filter and duplexer and power supply circuits. With the range of 2.7~3.3V the operated chip revealed moderate power consumption of 42mA. The chip was well operated at the receiving frequency of 925~960MHz. Measurement result is similar to general RF receiving specification of the 900MHz digital mobile phone.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2018.06a
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• pp.50.2-50.2
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• 2018

The demand for steady and dependable power sources is very high in the field of sustainable energy because of the limited amount of fossil fuels reserves. Among several sustainable alternatives, solar energy may be the most efficient solution because it constitutes the largest renewable energy source. So far, the only practical way to store such large amounts of energy has been to use a chemical energy carrier likewise a fuel. In various solar energy to power conversion systems, the photoelectrochemical (PEC) splitting of water into hydrogen and oxygen by the direct use of solar energy is an ideal process. It is a renewable method of hydrogen production integrated with solar energy absorption and water electrolysis using a single photoelectrode. Previous studies on photoelectrode films for PEC water splitting cells have been mainly focused on synthesizing oxide semiconductors with wide band gaps, such as TiO2(3.2eV), WO3(2.8eV), and Fe2O3(2.3eV). Unfortunately, these pristine oxide photoanodes without any catalysts have relatively low photocurrent densities because of the inherent limitation of insufficient visible light absorption due to the wide bandgap. Specifically, there is a tradeoff between high photocurrent and photoelectrochemical corrosion behavior, which is representative of figures of meritf or PEC materials.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.4
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• pp.152-161
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• 1996

In tis work, a three-stage pipelined A/D converter (ADC) was implemented to obtain 10-bit resolution at a conversion rate of 20 msamples/s for video applications. The ADC consists of three identical stages employing a mid-rise coding technique. The interstage errors such as offsets and clock feedthrough are digitally corrected in digitral logic by one overlapped bit between stages. The proposed ADC is optimized by adopting a unit-capacitor array architecture in the MDAC to improve the differential nonlinearity and the yield. Reduced power dissipation has been achieve dby using low-power latched comparators. The prototype was fabricated in a 0.8$\mu$m p-well CMOS technology. The ADC dissipates 160 mW at a 20 MHz clock rate with a 5 V single supply voltage and occupies a die area of 7 mm$^{2}$(2.7 mm $\times$ 2.6mm) including bonding pads and stand-alone internal bias circuit. The typical differential and integral nonlinarities of the prototype are less than $\pm$ 0.6 LSB and $\pm$ 1 LSB, respectively.