• Title/Summary/Keyword: single power-conversion

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Capacitor Ratio-Independent and OP-Amp Gain-Insensitive Algorithmic ADC for CMOS Image Sensor (커패시터의 비율과 무관하고 OP-Amp의 이득에 둔감한 CMOS Image Sensor용 Algorithmic ADC)

  • Hong, Jaemin;Mo, Hyunsun;Kim, Daejeong
    • Journal of IKEEE
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    • v.24 no.4
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    • pp.942-949
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    • 2020
  • In this paper, we propose an improved algorithmic ADC for CMOS Image Sensor that is suitable for a column-parallel readout circuit. The algorithm of the conventional algorithmic ADC is modified so that it can operate as a single amplifier while being independent of the capacitor ratio and insensitive to the gain of the op-amp, and it has a high conversion efficiency by using an adaptive biasing amplifier. The proposed ADC is designed with 0.18-um Magnachip CMOS process, Spectre simulation shows that the power consumption per conversion speed is reduced by 37% compared with the conventional algorithmic ADC.

The Three-Level Converter using IM(Integrated Magnetics) method (IM(Integrated Magnetics) 방식을 이용한 Three-Level 컨버터)

  • Bae, Jin-Yong;Kim, Yong;Kwon, Soon-Do;Eom, Tae-Min
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.22 no.4
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    • pp.35-45
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    • 2008
  • This paper present the Three-Level converter using IM(Integrated Magnetics) method for high power application. In power conversion system, magnetic components are important devices used for energy storage, energy transfer, galvanic isolation and filtering. The proposed Three-Level converter is to reduce the number of magnetic components using transformer integrated with output inductor. This paper proposes reluctance model base on the magnetic analysis for the Three-Level converter. Also, the secondary rectification was discussed by a single core transformer winding. A protype featuring 540[V] input, 48[V] output, 40[kHz] switching frequency, and 3[kW] output power using IGBT.

Development of a Computer Code for Low-and Intermediate-Level Radioactive Waste Disposal Safety Assessment

  • Park, J.W.;Kim, C.L.;Lee, E.Y.;Lee, Y.M.;Kang, C.H.;Zhou, W.;Kozak, M.W.
    • Journal of Radiation Protection and Research
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    • v.29 no.1
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    • pp.41-48
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    • 2004
  • A safety assessment code, called SAGE (Safety Assessment Groundwater Evaluation), has been developed to describe post-closure radionuclide releases and potential radiological doses for low- and intermediate-level radioactive waste (LILW) disposal in an engineered vault facility in Korea. The conceptual model implemented in the code is focused on the release of radionuclide from a gradually degrading engineered barrier system to an underlying unsaturated zone, thence to a saturated groundwater zone. The radionuclide transport equations are solved by spatially discretizing the disposal system into a series of compartments. Mass transfer between compartments is by diffusion/dispersion and advection. In all compartments, radionuclides ate decayed either as a single-member chain or as multi-member chains. The biosphere is represented as a set of steady-state, radionuclide-specific pathway dose conversion factors that are multiplied by the appropriate release rate from the far field for each pathway. The code has the capability to treat input parameters either deterministically or probabilistically. Parameter input is achieved through a user-friendly Graphical User Interface. An application is presented, which is compared against safety assessment results from the other computer codes, to benchmark the reliability of system-level conceptual modeling of the code.

Methodology of seismic-response-correlation-coefficient calculation for seismic probabilistic safety assessment of multi-unit nuclear power plants

  • Eem, Seunghyun;Choi, In-Kil;Yang, Beomjoo;Kwag, Shinyoung
    • Nuclear Engineering and Technology
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    • v.53 no.3
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    • pp.967-973
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    • 2021
  • In 2011, an earthquake and subsequent tsunami hit the Fukushima Daiichi Nuclear Power Plant, causing simultaneous accidents in several reactors. This accident shows us that if there are several reactors on site, the seismic risk to multiple units is important to consider, in addition to that to single units in isolation. When a seismic event occurs, a seismic-failure correlation exists between the nuclear power plant's structures, systems, and components (SSCs) due to their seismic-response and seismic-capacity correlations. Therefore, it is necessary to evaluate the multi-unit seismic risk by considering the SSCs' seismic-failure-correlation effect. In this study, a methodology is proposed to obtain the seismic-response-correlation coefficient between SSCs to calculate the risk to multi-unit facilities. This coefficient is calculated from a probabilistic multi-unit seismic-response analysis. The seismic-response and seismic-failure-correlation coefficients of the emergency diesel generators installed within the units are successfully derived via the proposed method. In addition, the distribution of the seismic-response-correlation coefficient was observed as a function of the distance between SSCs of various dynamic characteristics. It is demonstrated that the proposed methodology can reasonably derive the seismic-response-correlation coefficient between SSCs, which is the input data for multi-unit seismic probabilistic safety assessment.

A FG-CPW Single Balanced Diode Mixer for C-Band Application (C-Band 용 FG-CPW 단일 평형 다이오드 혼합기)

  • Bae, Joung-Sun;Lee, Jong-Chul;Kim, Jong-Heon;Lee, Byung-Je;Kim, Nam-Young
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.12 no.3
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    • pp.339-345
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    • 2001
  • In this paper, FG-CPW (Finite-Ground Coplanar Wave-Guide) balanced diode mixer is presented. Frequency bandwidth is selected for a C-band, which is 5.72~5.82 GHz for RF, 5.58~5.68 GHz for LO, and 140 MHz for IF signals. A rat-race hybrid is designed for the accomplishment of single balanced type. A low pass filter (LPF) with CPW structure is used far good conversion loss and unwanted harmonics suppression. When LO signal with the power of 4 dBm at 5.635 GHz is injected, a conversion loss of 6.2 dB is obtained for the mixer. Also, the LO to RF and LO to IF isolation of 30 dB and 40 dB are obtained, respectively. This mixer can be used in the area on wireless LAN application.

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Manufacture of a single gate MESFET mixer at PCS frequency band (PCS 주파수 대역 단일 게이트 MESFET 혼합기의 제작)

  • 이성용;임인성;한상철;류정기;오승엽
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.9 no.1
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    • pp.25-33
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    • 1998
  • In this paper, we describe a single-gate MESFET mixer at PCS(Personal Communication Service) frequency band. The PCS frequency band is 1965~2025 MHz in FR and 140 MHz in IF irrespectly. The design of the mixer was executed by microwave simulator, EEsof Libra. The matching network is consisted of rectangular inductor, MIM capacitor and open stub. The ma- nufacture work was accomplished by the micro-pen and wedge-bonder. The mixer showed $6.69\pm0.65$ dB of conversion gain, $-14.9\pm3.5$dB of RF reflection coefficient and 57.83 dB of LO/IF isolation at 10 dBm of LO power when LO frequency is 1855 MHz. When this mixer is used at PCS terminal, IF-amplifier which compensates the conversion loss of diode mixer may be omitted.

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The Output Characteristics of Low Repetition·High Power Nd:YAG Laser Using LLC Resonant Converter (LLC 공진형 컨버터를 활용한 저 반복·고출력 Nd:YAG 레이저의 출력특성)

  • Lee, Hee-Chang
    • Journal of Advanced Marine Engineering and Technology
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    • v.39 no.3
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    • pp.286-291
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    • 2015
  • LLC resonant converter is used to control laser output power in Nd:YAG laser. Zero voltage switching (ZVS) is implemented to minimize the switching loss which is adopting the LLC resonant converter. In the spot welding processing of metal thin films, the processing quality is decided by the laser beam output energy of single pulse. We decide to the 50 [J] as the single pulse laser beam energy. Laser output power is investigated and experimented by changing the output current. That current is controled by the charging voltage of capacitor. From those results, we obtained the maximum laser output of 58.2 [J] and the conversion efficiency of 2.52% at the discharge voltage of 620V and the discharge current of 861 [A] and the pulse repetition rate of 1 [Hz] at the charging capacitor of 12,000 [${\mu}F$].

Design of a 24 GHz Power Amplifier Using 65-nm CMOS Technology (65-nm CMOS 공정을 이용한 24 GHz 전력증폭기 설계)

  • Seo, Dong-In;Kim, Jun-Seong;Cui, Chenglin;Kim, Byung-Sung
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.27 no.10
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    • pp.941-944
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    • 2016
  • This paper proposes 24 GHz power amplifier for automotive collision avoidance and surveillance short range radar using Samsung 65-nm CMOS process. The proposed circuit has a 2-stage differential power amplifier which includes common source structure and transformer for single to differential conversion, impedance matching, and power combining. The measurement results show 15.5 dB maximum voltage gain and 3.6 GHz 3 dB bandwidth. The measured maximum output power is 13.1 dBm, input $P1_{dB}$ is -4.72 dBm, output $P1_{dB}$ is 9.78 dBm, and maximum power efficiency is 17.7 %. The power amplifier consumes 74 mW DC power from 1.2 V supply voltage.

Design of Single-Inductor Dual-Output Boost-Boost DC-DC Converter with Dual Feedback Loop Based on Relative Sawtooth Generator (Dead-time을 갖는 톱니파 발생기를 이용한 이중 피드백 루프 기반 단일 인덕터 이중 출력 승압형 변압기 설계)

  • Yun, Dam;Kim, Dong-Young;Lee, Kang-Yoon
    • Journal of IKEEE
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    • v.18 no.2
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    • pp.220-227
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    • 2014
  • This paper presents a control method of Single-Inductor Dual-Output DC-DC Converter using Common mode feedback and differential feedback loops. To generate duty used for differential mode feedback loop, this paper propose relative sawtooth circuit using current divider circuit which makes ramp signal with variable dead-time. Two outputs of the Single-Inductor Dual-Output DC-DC Converter are specified for 2.8 V and 4.2 V with input voltage 2.5 V. The maximum conversion efficiency of designed SIDO DC-DC Converter is 95% at total output power of 539mW. Cross regulations of Boost1 and Boost2 are 3.57% and 4% each, when increasing twice times output current.

Design and Implementation of a Near Zero IF Sub-harmonic Cascode FET Mixer for 2.4 GHz WLL Base-Station (Near Zero IF를 갖는 2.4 GHz WLL 기지국용 하모닉 Cascode FET 혼합기 설계 및 제작)

  • Lee, Hyok;Jeong, Youn-Suk;Kim, Jeong-Pyo;Choi, Jea-Hoon
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.14 no.5
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    • pp.472-478
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    • 2003
  • In this paper, a near zero If mixer was designed in cascode structure by using two single-gate FETs. Since it is driven by the second order harmonic of LO signal, a sub-harmonic cascode FET mixer has good LO-RF port isolation characteristic. In order to solve DC offset of a homodyne system, near zero If is used instead of zero If and the mixer is driven by sub-harmonic of LO signal. As RF input power was -30 dBm and LO power was 6 dBm, the designed mixer had 6.7 dB conversion gain, 8.4 dB noise figure, 31.5 dB LO-RF port isolation, -1.9 dBm lIP3 and -2.8 dBm IIP2.