• 한국경영과학회지
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• 제4권1호
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• pp.41-51
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• 1979

The Classical multi-server heterogeneous queuing system can be more generalized by using the concept of the switching rules. The descriptions of these systems, the relations among the state probebilities at the various points of interest, and comparisons with the single-server system will be presented. Instead of using the imbedded markov chain we set up the simultaneous equations for the state probabilites by the supplementary variable method.

• Journal of the Korean Data and Information Science Society
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• 제28권2호
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• pp.451-459
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• 2017

There are many researches showing that when a process change has occurred, variable sampling intervals (VSI) control chart is better than the fixed sampling interval (FSI) control chart in terms of reducing the required time to signal. When the process engineers use VSI control procedure, frequent switching between different sampling intervals can be a complicating factor. However, average number of samples to signal (ANSS), which is the amount of required samples to signal, and average time to signal (ATS) do not provide any control statistics about switching performances of VSI charts. In this study, we evaluate numerical switching performances of multivariate VSI EWMA chart including average number of switches to signal (ANSW) and average switching rate (ASWR). In addition, numerical study has been carried out to examine how to improve the performance of considered chart with accumulate-combine approach under several different smoothing constant and sample size. In conclusion, process engineers, who want to manage the correlation coefficients of related quality variables, are recommended to make sample size as large and smoothing constant as small as possible under permission of process conditions.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제50권4호
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• pp.188-200
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• 2001

This paper presents a technique for reconstructing converter line currents using the information from a single current sensor in the DC-link for voltage-source PWM converters. When three-Phase input currents cannot be reconstructed, three methods to acquire the input current are compared. Two of them are methods of modifying the switching state (I, II), another is a method of using the predictive state observer. Also, compensation of sampling delay, and a simultaneous sample value of input currents in the center of a switching period are included. Suitable criteria for the comparison are identified, and the differences in the performance of these methods are investigated through experimental results for a typical V-S PWM converter rated at 10kVA.

• Journal of the Korean Data and Information Science Society
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• 제26권6호
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• pp.1593-1600
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• 2015

A control chart is very useful in monitoring various production process. There are many situations in which the simultaneous control of two or more related quality variables is necessary. We construct bivariate Shewhart control charts based on the trace of the product of the estimated variance-covariance matrix and the inverse of the in-control matrix and investigate the properties of bivariate Shewart control charts with VSI procedure for monitoring covariance matrix in term of ATS (Average time to signal) and ANSW (Average number of switch) and probability of switch, ASI (Average sampling interval). Numerical results show that ATS is smaller than ARL. From examining the properties of switching in changing covariances and variances in ${\Sigma}$, ANSW values show that it does not switch frequently and does not matter to use VSI procedure.

• 대한전자공학회논문지SD
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• 제41권1호
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• pp.71-80
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• 2004

본 논문에서는 집적회로 패키지에 기인한 노이즈를 해석할 수 있는 새로운 SSN모델을 보인다. 기존의 디커플링 커패시터를 고려하지 않은 회로모델은 과도하게 SSN을 예측한다는 것을 보였으며, 디커플링 커패시터가 포함된 패키지 회로모델을 통하여 새로운 SSN 모델을 제안하였다. 새롭게 제안된 SSN 모델은 0.18um공정(TSMC 0.18um공정)을 사용하여 다양한$\cdot$회로설계 변수(입력상승시간, 패키지 인덕턴스 및 동시 스위칭 개수)의 변화에 따라 HSPICE 시뮬레이션과 정확히($5\%$ 이내에서) 일치한다는 것을 검증하였다.

• 한국정보처리학회논문지
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• 제7권7호
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• pp.2179-2187
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• 2000

This paper provides a heuristic analysis technique which determines an optimal number of V\ulcorner/V\ulcorner pads meeting allowable Simultaneous Switching Noise(SN) budget, early in the design phase. Until now, in determining the number of V\ulcorner/V\ulcorner pads, designers had to simulate packaging models case by case in the design phase or roughly allocate the power/ground pins in an inaccurate way according to typical design rules. However, due to the high density and frequency trends of IC technologies, the V\ulcorner/V\ulcorner pads allocation method can affect an adverse effect on IC operations, which requires more accurate and efficient methods be devised. Thus, this paper proposes an analytic V\ulcorner/V\ulcorner pads calculation method that gives a practical help for packaging designs early in the design phase. The proposed method is applied to a design example of a 1/8x208 pin plastic quad flat package (PQFP) and the results are verified through simulation using HSPICE.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제10권9호
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• pp.4223-4239
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• 2016

In this paper, we consider an amplify-and-forward (AF) full-duplex relay network (FDRN) using simultaneous wireless information and power transfer, where a battery-free relay node harvests energy from the received radio frequency (RF) signals from a source node and uses the harvested energy to forward the source information to destination node. The time-switching relaying (TSR) protocol is studied, with the assumption that the channel state information (CSI) at the relay node is imperfect. We deliver a rigorous analysis of the outage probability of the proposed system. Based on the outage probability expressions, the optimal time switching factor are obtained via the numerical search method. The simulation and numerical results provide practical insights into the effect of various system parameters, such as the time switching factor, the noise power, the energy harvesting efficiency, and the channel estimation error on the performance of this network. It is also observed that for the imperfect CSI case, the proposed scheme still can provide acceptable outage performance given that the channel estimation error is bounded in a permissible interval.

• Journal of Power Electronics
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• 제15권2호
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• pp.299-308
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• 2015

This study proposes four novel pulse width modulation (PWM) shoot-through control methods for impedance source (IS) galvanically isolated DC-DC converters. These methods are derived from a PWM control method with shifted shoot-through introduced by the authors in 2012. In contrast to the baseline solution, where the shoot-through states are generated by the simultaneous conduction of all transistors in the inverter bridge, our new approach is based on the shoot-through generation by one inverter leg. The idea is to increase the number of soft-switched transients and, therefore, decrease the dynamic losses of the front-end inverter. All the proposed approaches are experimentally verified through an insulated-gate bipolar transistor-based IS DC-DC converter. Conclusions are drawn in accordance with the results of the switching loss analysis.

• 전력전자학회논문지
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• 제22권2호
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• pp.166-174
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• 2017

This study proposes a compensation method for the dead-time effects on a single-phase grid-connected inverter. Dead time should be considered in the pulse-width modulation gating signals to prevent the simultaneous conduction of switching devices, considering that a switching device has a finite switching time. Consequently, the output current of the grid-connected inverter contains odd-numbered harmonics because of the dead time and the nonlinear characteristics of the switching devices. The effects of dead time on output voltage and current are analyzed in this study. A new compensation algorithm based on second-order generalized integrator is also proposed to reduce the dead-time effect. Simulation and experimental results validate the effectiveness of the proposed compensation algorithm.

• 대한전자공학회논문지SD
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• 제43권12호
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• pp.23-32
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• 2006

다층 고속 디지털 보드에 대한 빠르고 정확한 전압 버스 설계 방법은 정확하고 정밀한 고속 보드에 전원 공급망 설계 방법을 위해 고안되었다. FAPUD는 PBEC(Path Based Equivalent Circuit)모델과 망 합성 방법의 두 중요 알고리즘을 기반으로 구성된다. PBEC 모델 기반의 회로 레벨의 2차원 전원 분배 망의 전기적 값으로부터 lumped 1차원 회로 모델로 간단한 산술 표현들을 활용한다 제안된 PBEC 기반인 회로 단계 설계는 제안한 지역 접근법을 이용해 수행된다. 이 회로 단계 설계는 온칩 디커플링 커패시터의 크기, 오프칩 디커플링 커패시터의 위치와 크기, 패키지 전압 버스의 유효한 인덕턴스를 직접 결정하고 계산한다. 설계 출력에 따라 모든 디커플링 커패시터가 포한된 lumped 회로 모델과 전압 버스의 레이아웃은 FAPUD 방법을 이용한 후 얻을 수 있다. 미세조정 과정에서, I/O Switching에 의해 덧붙여진 Simultaneous Switching Noise(SSN)를 고려한 보드 재 최적화가 수행될 수 있다 이는 전원 공급 잡음에 I/O 동작 효과가 lumped 회로 모델을 가지고 전 동작 주파수 범위에 대해 추산될 수 있기 때문이다. 게다가 만약 설계에 조정이 필요하거나 교체해야 한다면, FAPUD 방법은 다른 전면 설계변경 없이 디커플링 커패시터들을 대체하여 설계를 수정하는 것이 가능하다. 마지막으로 FAPUD 방법은 전형적인 PEEC 기본설계 방법과 비교해 정확하고 FAPUD 방법의 설계 시간은 전형적인 PEEC 기본 설계 방법의 시간보다 10배가 빠르다.