• Journal of Electrical Engineering and information Science
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• v.2 no.6
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• pp.212-216
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• 1997

A new metal tip fabrication process for low voltage operation is reported in this paper. The key element of the fabrication process is that isotropic silicon etching and oxidation process used in silicon tip fabrication is utilized for gate hole size reduction and gate oxide layer. A metal FEA with 625 tips was fabricated in order to demonstrate the validity of the new process and submicron gate apertures were successfully obtained from originally 1.7$\mu\textrm{m}$ diameter mask. The emission current above noise level was observed at the gate bias of 50V. The required gate voltage to obtain the anode current of 0.1${\mu}\textrm{A}$/tip was 74V and the emission current was stable above 2${\mu}\textrm{A}$/tip without any disruption. The local field conversion factor and the emitting area were calculated as 7.981${\times}$10\ulcornercm\ulcorner and 3.2${\times}$10\ulcorner$\textrm{cm}^2$/tip, respectively.

• Journal of Welding and Joining
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• v.28 no.6
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• pp.40-44
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• 2010

Laser assisted machining (LAM) has been researched in order to machine the silicon nitride ceramics economically and effectively. LAM is an effective machining method by local heating of the cutting part to the softening temperature of the silicon nitride using laser beam. When silicon nitride ceramics is heated using a laser beam, the surface of silicon nitride ceramic is softened, oxidized and decomposed. And then surface hardness is decreased. Through machining in low viscosity and hardness conditions, silicon nitride was machined effectively and the life span of tool was increased. The plastic deformation was occurred due to softening of amorphous YSiAlON above $ 1,000^{\circ}C$. Transgranular fracture of ${\beta}-Si_3N_4$ was occurred when YSiAlON was not softened, but mostly intergranular fracture was occurred by the plastic deformation of softened YSiAlON.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.11a
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• pp.126-127
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• 2005

Semiconductor carbon nanotube was grown on oxided silicon wafer with Atmosphere Pressure Chemical Vapor Deposition (APCVD) ethmod and investigated the electrical property after thermal oxidation at 300$^{\circ}C$ in air. The electrical property was measured at room temperature in air after thermal oxidation at 300$^{\circ}C$ for various times in air. Semiconductor carbon nanotube was steadily changed to metallic carbon nanotube as increasing of thermal oxidation times at 300$^{\circ}C$ in air.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.3
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• pp.181-185
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• 2003

Influence of post gate oxidation anneal on Negative Bias Temperature Instability (NBTI) of PMOSFE has been investigated. At oxidation anneal temperature raised above 950$^{\circ}$C, a significant improvement of NBTI was observed which enables to reduce PMO V$\_$th/ shift occurred during a Bias Temperature (BT) stress. The high temperature anneal appears to suppress charge generations inside the gate oxide and near the silicon oxide interface during the BT stress. By measuring band-to-band tunneling currents and subthreshold slopes, reduction of oxide trapped charges and interface states at the high temperature oxidation anneal was confirmed.

• Korean Journal of Materials Research
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• v.3 no.1
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• pp.7-11
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• 1993

Abstract Oxidation kinetics of silicon oxide films formed by rapid thermal oxidizing Si substrate in $N_2$O ambient studied. The data on $N_2$0 oxidation shows that the interfacial nitrogen-rich layers results in oxide growth in the parabolic regime by impeding oxidant diffusion to the Si$O_2$-Si interface even for ultrathin oxides. The activation energy of parablic rate constant, B, is about 1.5 eV, and the energy increses with oxide thickness.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.8
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• pp.708-713
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• 2005

An alumina membrane with nano-sized pore array by anodic oxidation using the thin film aluminum deposited on silicon wafer was fabricated. It Is important that the sample prepared by metal deposition method has a flat aluminum surface and a good adhesion between the silicon wafer and the thin film aluminum. The oxidation time was controlled by observation of current variation. While the oxalic acid with 0.2 M was used for low voltage anodization under 100 V, the chromic acid with 0.1 M was used for high voltage anodization over 100 V. The nano-sized pores with diameter of $60\~120$ nm was obtained by low voltage anodization of $40\~80$ V and those of $200\~300$ nm was obtained by high voltage anodization of $140\~200$ V. The pore widening process was employed for obtaining the one-channel with flat surface because the pores of the alumina membrane prepared by the fixed voltage method shows the structure of two-channel with rough surface. Finally, the sample was immersed to the phosphoric acid with 0.1 M concentration to etching the barrier layer.

• Journal of the Korean institute of surface engineering
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• v.32 no.6
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• pp.695-702
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• 1999

We have explored the factors affecting the resistivity of Cu (Mg) alloy, which was prepared by sputtering. The results show that the resistivity is a function of Mg content, annealing temperature, annealing time, and Cu-alloy thickness. Addition of Mg to copper increases the resistivity through solute scattering. In addition, increasing Mg content promotes the interfacial reaction between Mg and SiO$_2$ to produce the free silicon and the generated free silicon dissolves into copper, resulting in a significant increase of resistivity. Furthermore, increasing oxidation temperature rapidly decreases the resistivity at the initial stage of oxidation and then continues to increase the resistivity to the saturation value with increasing oxidation time. The saturation value depends on the residual Mg content and the thickness of the alloy. TEM and AES analyses reveal that dense, uniform MgO grows to the limiting thickness of about $150\AA$. However, interfacial MgO does not show the limiting thickness, instead continues to grow until Mg is completely exhausted. From these facts, we proposed the maximum available Mg content needed to from the dense MgO on the surface and suppress the excessive interfacial reaction.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.120-122
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• 2005

An alumina membrane with nano-sized pore array by anodic oxidation using thin film aluminum deposited on silicon wafer was fabricated. It is important that the sample prepared by metal deposition method has a flat aluminum surface and a good adhesion between the silicon wafer and the thin film aluminum. The oxidation time was controlled by observation of current variation. While the oxalic acid with 0.2M was used for low voltage anodization under 100V, the chromic acid with 0.1M was used for high voltage anodization over 100V. The nano-sized pores with diameter of 60~120nm was obtained by low voltage anodization of 40~90V and those of 200~300nm was obtained by high voltage anodization of 120~160V. Finally, the sample was immersed to the phosphoric acid with 0.1M concentration to etching the barrier layer. The sample will be applied to electronic sensors, field emission display, and template for nano-structure.

• Korean Journal of Metals and Materials
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• v.50 no.8
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• pp.575-582
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• 2012

Medium carbon steel was aluminized by hot dipping into molten Al or Al-1 at% Si baths. After hot-dipping in these baths, a thin Al-rich topcoat and a thick alloy layer rich in $Al_5Fe_2$ formed on the surface. A small amount of FeAl and $Al_3Fe$ was incorporated in the alloy layer. Silicon from the Al-1 at% Si bath was uniformly distributed throughout the entire coating. The hot dipping increased the microhardness of the steel by about 8 times. Heating at $700-1000^{\circ}C$, however, decreased the microhardness through interdiffusion between the coating and the substrate. The oxidation at $700-1000^{\circ}C$ in air formed a thin protective ${\alpha}-Al_2O_3$ layer, which provided good oxidation resistance. Silicon was oxidized to amorphous silica, exhibiting a glassy oxide surface.

• Journal of Convergence for Information Technology
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• v.11 no.11
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• pp.159-165
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• 2021

A fin channel with a fin width of 20 nm and a gradually increased source/drain extension regions are fabricated on a bulk silicon wafer by using a three-dimensional selective oxidation. The detailed process steps to fabricate the proposed fin channel are explained. We are demonstrating their preliminary characteristics and properties compared with those of the conventional fin field effect transistor device (FinFET) and the bulk FinFET device via three-dimensional device simulation. Compared to control devices, the three-dimensional selective oxidation fin channel MOSFET shows a higher linear transconductance, larger drive current, and lower series resistance with nearly the same scaling-down characteristics.