• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.105-110
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• 2008

We have proposed a new structure of poly-silicon thin film transistor(TFT) which was fabricated the LDD region using doping oxide with graded spacer by etching shape retio. The devices of n-channel poly-si TFT's hydrogenated by $H_2$ and $HT_2$/plasma processes are fabricated for the devices reliability. We have biased the devices under the gate voltage stress conditions of maximum leakage current. The parametric characteristics caused by gate voltage stress conditions in hydrogenated devices are investigated by measuring /analyzing the drain current, leakage current, threshold voltage($V_{th}$), sub-threshold slope(S) and transconductance($G_m$) values. As a analyzed results of characteristics parameters, the degradation characteristics in hydrogenated n-channel polysilicon TFT's are mainly caused by the enhancement of dangling bonds at the poly-Si/$SiO_2$ interface and the poly-Si Brain boundary due to dissolution of Si-H bonds. The structure of novel proposed poly-Si TFT's are the simplity of the fabrication process steps and the decrease of leakage current by reduced lateral electric field near the drain region.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.1-5
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• 2010

We developed a novel micro-electro mechanical systems (MEMS) test socket using silicon on insulator (SOI) substrate with the cantilever array structure. We designed the round shaped cantilevers with the maximum length of $350{\mu}m$, the maximum width of $200{\mu}m$ and the thickness of $10{\mu}m$ for $650{\mu}m$ pitch for 8 mm x 8 mm area and 121 balls square ball grid array (BGA) packages. The MEMS test socket was fabricated by MEMS technology using metal lift off process and deep reactive ion etching (DRIE) silicon etcher and so on. The MEMS test socket has a simple structure, low production cost, fine pitch, high pin count and rapid prototyping. We verified the performances of the MEMS test sockets such as deflection as a function of the applied force, path resistance between the cantilever and the metal pad and the contact resistance. Fabricated cantilever has 1.3 gf (gram force) at $90{\mu}m$ deflection. Total path resistance was less than $17{\Omega}$. The contact resistance was approximately from 0.7 to $0.75{\Omega}$ for all cantilevers. Therefore the test socket is suitable for BGA integrated circuit (IC) packages tests.

• Korean Chemical Engineering Research
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• v.44 no.5
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• pp.513-519
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• 2006

We developed two kinds of the microchip for application to electrophoresis based on both glass and quartz employing the MEMS fabrications. The poly-Si layer deposited onto the bonding interface apart from channel regions can play a role as the optical slit cutting off the stray light in order to concentrate the UV ray, from which it is possible to improve the signal-to-noise (S/N) ratio of the detection on a chip. In the glass chip, the deposited poly-Si layer had an important function of the etch mask and provided the bonding surface properly enabling the anodic bonding. The glass wafer including more impurities than quartz one results in the higher surface roughness of the channel wall, which affects subsequently on the microflow behavior of the sample solutions. In order to solve this problem, we prepared here the mixed etchant consisting HF and $NH_4F$ solutions, by which the surface roughness was reduced. Both the shape and the dimension of each channel were observed, and the electroosmotic flow velocities were measured as 0.5 mm/s for quartz and 0.36 mm/s for glass channel by implementing the microchip electrophoresis. Applying the optical slit with poly-Si layer provides that the S/N ratio of the peak is increased as ca. 2 times for quartz chip and ca. 3 times for glass chip. The maximum UV absorbance is also enhanced with ca. 1.6 and 1.7 times, respectively.

• Journal of the Korean Vacuum Society
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• v.6 no.3
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• pp.220-226
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• 1997

An optical intensity-type pressure sensor has been fabricated by coupling multimode optical fiber with 100 nm-Au/30 nm-NiCr/150 nm-$Si_3N_4/300 nm-SiO_2/150 nm-Si_3N_4$ optical reflection layer supported by micromachined frame-shape silicon substrate, and its characteristics was investigated. For the application of $Si_3N_4/SiO_2/Si_3N_4$ diaphragm to the optical reflection layer of the sensor, NiCr and Au films were deposited on the backside of the diaphragm by thermal evaporation , respectively, and thus optical low caused by transmission in the reflection layer could be decreased to a few percents. Dielectric diaphragms with uniform thickness were able to be also reproduced because top- and bottom-$Si_3N_4$ layer of the diaphragm could automatically stop silicon anisotropic etching. The respective pressure ranges in which the sensor showed linear optical output power-pressure characteristics were 0~126.64 kPa, 0~79. 98 kPa, and 0~46.66 kPa, and the respective pressure sensitivities of the sensor were about 20.69 nW/kPa, 26.70 nW/kPa, and 39.33 nW/kPa, for the diaphragm sizes of 3$\times$3 $\textrm{mm}^2$, 4$\times$4 $\textrm{mm}^2$, and 5$\times$5 $\textrm{mm}^2$, indicating that the sensitivity increases as diaphragm size increases.

• Journal of Sensor Science and Technology
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• v.8 no.3
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• pp.283-290
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• 1999

The $n^+/p/p^+$ junction PERL solar cell of $0.1{\sim}2{\Omega}{\cdot}cm$ (100) p type silicon wafer was fabricated through the following steps; that is, wafer cutting, inverted pyramidally textured surfaces etching by KOH, phosphorus and boron diffusion, anti-reflection coating, grid formation and contact annealing. At this time, the optical characteristics of device surface and the efficiency of doping concentration for resistivity were investigated. And diffusion depth and doping concentration for n+ doping were simulated by silvaco program. Then their results were compared with measured results. Under the illumination of AM (air mass)1.5, $100\;mW/cm^2$ $I_{sc}$, $V_{oc}$, fill factor and the conversion efficiency were 43mA, 0.6 V, 0.62. and 16% respectively.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.2
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• pp.808-816
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• 2012

This paper is the study for the directional solidification of the ingot through the thermal analysis simulation and structural change of casting furnace. With the results of thermal analysis simulation, the silicon as a whole has reached the melting temperature as the retention time 80 min. The best cooling conditions showed at the upper cooling temperature $1,400^{\circ}C$ and cooling time 60min. The fabricated wafers showed the superior etching result at the grain boundary than that of existing commercial wafers. The FTIR measurements of oxygen and carbon impurities were not in the critical value for solar conversion efficiency. The NAA analysis of metal impurities were also detected the total number of 18 different metals, but the concentration distribution showed no significant positional deviations in the same position from the top to the bottom.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.615-618
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• 2005

In this work, the effects of corner transistors in SOI MOSFETs were investigated. We fabricated SOI MOSFETs with various widths and a fixed length and characterized them. The SOI thickness was $4000{\AA}$ and the buried oxide(BOX) thickness was $4000{\AA}$. The isolation of active region was simply done by silicon etching and TEOS sidewall formation. Several undesirable characteristics have been reported for LOCOS isolation in fabrication on SOI wafers so far. Although we used an STI-like process instead of LOCOS, there were still a couple of abnormal phenomena such as kinks and double humps in drain current. Above all, we investigated the location of the parasitic transistors and found that they were at the corners of the SOI in width direction by high-resolution SEM inspection. It turned out that their characteristics are strongly dependent on the channel width. We made a contact pad through which we can control the body potential and figured out the dependency of operation on the body potential. The double humps became more prominent as the body bias went more negative until the full depletion of the channel where the threshold voltage shift did not occur any more. Through these works, we could get insights on the process that can reduce the effects of corner transistors in SOI MOSFETs, and several possible solutions are suggested at the end.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.262-262
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• 2016

최근 고해상도 디스플레이가 주목받으면서 기존 비정질 실리콘(a-Si)을 대체할 수 있는 재료에 관한 연구가 활발히 진행되고 있다. a-Si의 경우 간단한 공정 과정, 적은 생산비용, 대면적화가 가능하다는 장점이 있지만 전자 이동도가 매우 낮은 단점이 있다. 반면, 산화물 반도체는 비정질 상태에서 전자 이동도가 높으며 큰 밴드갭을 가지고 있어 투명한 특성을 나타낼 뿐만 아니라, 저온공정이 가능하여 기판의 제한이 없는 장점을 가지고 있다. 대표적으로 가장 널리 연구되고 있는 산화물 반도체는 a-IGZO(amorphous indium-gallium-zinc oxide)이다. 그러나 InZnO(IZO) 기반의 산화물 반도체에서 carrier suppressor 역할을 하는 Ga(gallium)은 수요에 대한 공급이 원활하지 못하여 비싸다는 단점이 있다. 그러므로 경제적이면서 a-IGZO와 유사한 전기적 특성을 나타낼 수 있는 suppressor 물질이 필요하다. 따라서 본 연구에서는 IZO 기반의 산화물 반도체에서 Ga을 Hf(hafnium), Zr(zirconium), Si(silicon)으로 대체하여 용액증착(solution-deposition) 공정으로 각각의 채널층을 형성한 back-gate type의 박막 트랜지스터(thin-film transistor, TFT) 소자를 제작하였다. 용액증착 공정은 물질의 비율을 자유롭게 조절할 수 있고, 대기압의 조건에서도 공정이 가능하기 때문에 짧은 공정시간과 저비용의 장점이 있다. 제작된 소자는 p-type Si 위에 게이트 절연막으로 100 nm의 열산화막이 성장된 기판을 사용하였다. 표준 RCA 클리닝 후에 각 solution 물질을 spin coating 방식으로 증착하였다. 이후, photolithography, develop, wet etching의 과정을 거쳐 채널층 패턴을 형성하였다. 또한, 산화물 반도체의 전기적 특성을 향상시키기 위해서 후속 열처리 과정(post deposition annealing, PDA)은 필수적이다. CTA 방식은 높은 열처리 온도와 긴 열처리 시간의 단점이 있다. 따라서, 본 연구에서는 $100^{\circ}C$ 이하의 낮은 온도와 짧은 열처리 시간의 장점을 가지는 MWI (microwave irradiation)를 후속 열처리로 진행하였다. 그 결과, 각 물질로 구현된 소자들은 기존 a-IGZO와 비교하여 적은 양의 carrier suppressor로도 우수한 전기적 특성 및 안정성을 얻을 수 있었다. 따라서, Si, Hf, Zr 기반의 산화물 반도체는 기존의 Ga을 대체하여 저비용으로 디스플레이를 구현할 수 있는 IZO 기반 재료로 기대된다.

• Journal of Sensor Science and Technology
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• v.14 no.1
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• pp.22-27
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• 2005

A thermoelectric flow sensor for small quantity of gas flow rate was fabricated using silicon wafer semiconductor process and bulk micromachining technology. Evanohm R alloy heater and chromel-constantan thermocouples were used as a generation heat unit and sensing parts, respectively. The heater and thermocouples are thermally isolated on the $Si_{3}N_{4}/SiO_{2}/Si_{3}N_{4}$ laminated membrane. The characteristics of this sensor were observed in the flow rate range from 0.2 slm to 1.0 slm and the heater power from 0.72 mW to 5.63 mW. The results showed that the sensitivities $(({\partial}({\Delta}V)/{\partial}(\dot{q}));{\;}{\Delta}V$ : voltage difference, $\dot{q}$ : flow rate) were increased in accordance with heater power rise and decreasing of flow rate.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.20 no.2
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• pp.408-413
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• 1996

A self-diagnostic, air-damped, piezoresitive, cantilever-beam microaccelerometer has been designed, fabricated and tested for applications to automotive electronic airbag systems. A skew-symmetric proof-mass has been designed for self-diagnostic capability and zero transverse sensitivity. Two kinds of multi-step anisotropic etching processes are developed for beam thickness control and fillet-rounding formation, UV-curing paste has been used for sillicon-to-glass bounding. The resonant frequency of 2.07kHz has been measured from the fabricated devices. The sensitivity of 195 $\mu{V}$/g is obtained with a nonlinearity of 4% over $\pm$50g ranges. Flat amplitude response and frequency-proportional phase response have been obserbed, It is shown that the design and fabricaiton methods developed in the present study yield a simple, practical and effective mean for improving the performance, reliability as well as the reproducibility of the accelerometers.