• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.5
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• pp.924-930
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• 2015

In this paper, we propose a novel approach of low computational complexity to improve the speech quality of the small acoustic equipment in noisy environment. The conventional gain control algorithm suppresses the noise of input signal, and then the part of wide dynamic range compression (WDRC) amplifies the undesired signal. The proposed algorithm controls the gain of hearing aids according to speech present probability by using the output of a voice activity detection (VAD). The performance of the proposed scheme is evaluated under various noise conditions by using objective measurement and yields superior results compared with the conventional algorithm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.8
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• pp.896-902
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• 2016

In this paper, we investigate a minimum mean-squared error based nonlinear successive precoding method as a practical solution of dirty paper coding for multiuser downlink channels where each user has more than one antenna in the presence of other cell interference (OCI). Unlike conventional zero-forcing (ZF) based methods, the proposed scheme takes the OCI plus noise into account when suppressing the inter-cell multiuser interference, which results in improvement of the received signal-to-interference-plus-noise ratio. Simulation results show that the proposed scheme outperforms conventional methods in terms of sum rate for various OCI configurations.

• ETRI Journal
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• v.30 no.6
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• pp.826-832
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• 2008

The metal-ferroelectric-metal (MFM) capacitor in the ferroelectric random access memory (FeRAM) embedded RFID chip is used in both the memory cell region and the peripheral analog and digital circuit area for capacitance parameter control. The capacitance value of the MFM capacitor is about 30 times larger than that of conventional capacitors, such as the poly-insulator-poly (PIP) capacitor and the metal-insulator-metal (MIM) capacitor. An MFM capacitor directly stacked over the analog and memory circuit region can share the layout area with the circuit region; thus, the chip size can be reduced by about 60%. The energy transformation efficiency using the MFM scheme is higher than that of the PIP scheme in RFID chips. The radio frequency operational signal properties using circuits with MFM capacitors are almost the same as or better than with PIP, MIM, and MOS capacitors. For the default value specification requirement, the default set cell is designed with an additional dummy cell.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.8 no.10
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• pp.3302-3320
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• 2014

An allocation of sensing and reporting times is proposed to improve the sensing performance by scheduling them in an efficient way for cognitive radio networks with cluster-based cooperative spectrum sensing. In the conventional cooperative sensing scheme, all secondary users (SUs) detect the primary user (PU) signal to check the availability of the spectrum during a fixed sensing time slot. The sensing results from the SUs are reported to cluster heads (CHs) during the reporting time slots of the SUs and the CHs forward them to a fusion center (FC) during the reporting time slots of the CHs through the common control channels for the global decision, respectively. However, the delivery of the local decision from SUs and CHs to a CH and FC requires a time which does not contribute to the performance of spectrum sensing and system throughput. In this paper, a super-allocation technique, which merges reporting time slots of SUs and CHs to sensing time slots of SUs by re-scheduling the reporting time slots, has been proposed to sense the spectrum more accurately. In this regard, SUs in each cluster can obtain a longer sensing duration depending on their reporting order and their clusters except for the first SU belonged to the first cluster. The proposed scheme, therefore, can achieve better sensing performance under -28 dB to -10 dB environments and will thus reduce reporting overhead.

• Journal of Power Electronics
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• v.16 no.5
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• pp.1661-1668
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• 2016

A fixed off-time controlled high power factor ac-dc LED driver is proposed in this paper, which employs a novel zero-crossing-compensation (ZCC) circuit based on a fixed off-time controlled scheme. Due to the parasitic parameters of the system, the practical waveforms have a dead region. By detecting the zero-crossing boundary, the proposed ZCC circuit compensates the control signal VCOMP within the dead region, and is invalid above this region. With further optimization of the parameters KR and Kτ of the ZCC circuit, the dead zone can be eliminated and lower THD is achieved. Finally, the chip is implemented in HHNEC 0.5μm 5V/40V HVCMOS process, and a prototype circuit, delivering 7~12W of power to several 3-W LED loads, is tested under AC input voltage ranging from 85V to 265V. The test results indicate that the average total harmonic distortion (THD) of the entire system is approximately 10%, with a minimum of 5.5%, and that the power factor is above 0.955, with a maximum of 0.999.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.8 no.3
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• pp.522-527
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• 2007

In this paper, we propose an error control coding scheme for constant-amplitude multicode-biorthogonal modulation. The product code is appropriate to the constant-amplitude multicode-biorthogonal modulation for the bit error rate performance improvement. In the constant-amplitude multicode-biorthogonal modulation, the vertical redundant bits are used for the constant amplitude coding. The proposed product code can be constructed by using the additional horizontal redundant bits. The hardware complexity of the encoder/decoder pair is very low. The simulation results show that the bit error rate performance of the proposed coding scheme is improve

• Journal of Electrical Engineering and Technology
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• v.11 no.4
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• pp.829-838
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• 2016

This paper focuses on the engineering trade-offs in designing capacitor voltage balancing schemes for modular multilevel converters (MMC) HVDC: regulation performance and switching loss. MMC is driven by the on/off switch operation of numerous submodules and the key design concern is balancing submodule capacitor voltages minimizing switching transition among submodules because it represents the voltage regulation performance and system loss. This paper first introduces the state-of-the-art MMC-HVDC submodule capacitor voltage balancing methods reported in the literatures and discusses the trade-offs in designing these methods for HVDC application. This paper further proposes a submodule capacitor balancing scheme exploiting a control signal to flexibly interchange between the on-state and the off-state submodules. The proposed scheme enables desired performance-based voltage regulation and avoids unnecessary switching transitions among submodules, consequently reducing the switching loss. The flexibility and controllability particularly fit in high-level MMC HVDC applications where the aforementioned design trade-offs become more crucial. Simulation studies for MMC HVDC are performed to demonstrate the validity and effectiveness of the proposed capacitor voltage balancing algorithm.

• Journal of Electrical Engineering and Technology
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• v.13 no.3
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• pp.1251-1264
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• 2018

The systematic and effective design method of a Class-D current-source resonant inverter for use in an induction cooker with zero-ripple line current is presented. The design procedure is based on the principle of the Class-D current-source resonant inverter with a simplified load network model that is a parallel equivalent circuit. An induction load characterization is obtained from a large-signal excitation test-bench based on parallel load network, which is the key to an accurate design for the induction cooker system. Accordingly, the proposed scheme provides a systematic, precise, and feasible solution than the existing design method based on series-parallel load network under low-signal excitation. Moreover, a zero-ripple condition of utility-line input current is naturally preserved without any extra circuit or control. Meanwhile, a differential-mode input electromagnetic interference (EMI) filter can be eliminated, high power quality in utility-line can be obtained, and a standard-recovery diode of bridge-rectifier can be employed. The step-by-step design procedure explained with design example. The devices stress and power loss analysis of induction cooker with a parallel load network under large-signal excitation are described. A 2,500-W laboratory prototype was developed for $220-V_{rms}/50-Hz$ utility-line to verify the theoretical analysis. An efficiency of the prototype is 96% at full load.

• Journal of Korean Society of Transportation
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• v.20 no.2
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• pp.135-148
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• 2002

In this paper, a queue length calculation algorithm using image detectors has been proposed. The algorithm produces the queue length using a pair of image detectors installed both on upstream and on downstream of a corridor. In addition, a new framework for controlling the traffic signal system based on queue length has been presented. More specifically, the scheme of determining the cycle time and green split using the queue lengths has been proposed. To validate the results, a simulation study was conducted with a network environment. Results showed that the proposed method gave better operational performance than a traditional method. However, additional validation effort is necessary in order to apply the real traffic conditions.

• Proceedings of the KIEE Conference
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• 2008.10b
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• pp.217-218
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• 2008

Since the digital TV signal band is very wide ($54{\sim}806MHz$), the VCO used in the frequency synthesizer must also have a wide frequency tuning range. Multiple LC VCOs have been used to cover such wide frequency band. However, the chip area increases due to the increased number of integrated inductors. A general method for achieving both reduced VCO gain(Kvco) and wide frequency band is to use the switched-capacitor bank LC VCO. In this paper, a scheme is proposed to cover the full band using only one VCO. The RF VCO block designed using a 0.18um CMOS process consists of a wideband LC VCO with reduced variation of VCO gain and frequency steps. Buffers, divide-by-2 circuits and control logics the simulation results show that the designed circuit has a phase noise at 100kHz better than -106dBc/Hz throughout the signal band and consumes $9.5{\sim}13mA$ from a 1.8V supply.