• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.12
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• pp.54-61
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• 1997

An accurate extraction technique is developed to determine full euqivalent circuit parameters of Si MOSFETs using 1 set of measured S-parametes without complicated optimization process. This technique is based on the use of anlytic Z-parameters experessions for resistances and inductances and the Y-parameter ones for ntrinsic parameters. This accuracy is proved over the wide range of gate voltage by observing good agreement between measured and fitted Z-parameter equations and frequency-independent response of the extracted intrinsic parameters. Using this technique, gate voltage-dependencies of model parameters are obained in the saturation region and these results show the similar behavior to the short-channel effects expected from the device theory.

• Journal of Electrical Engineering and Technology
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• v.9 no.1
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• pp.247-253
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• 2014

In this paper, a new two dimensional (2D) analytical modeling and simulation for a Dual Material Double Gate tunnel field effect transistor (DMDG TFET) is proposed. The Parabolic approximation technique is used to solve the 2-D Poisson equation with suitable boundary conditions and analytical expressions for surface potential and electric field are derived. This electric field distribution is further used to calculate the tunnelling generation rate and thus we numerically extract the tunnelling current. The results show a significant improvement in on-current characteristics while short channel effects are greatly reduced. Effectiveness of the proposed model has been confirmed by comparing the analytical results with the TCAD simulation results.

• Korean Journal of Optics and Photonics
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• v.12 no.4
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• pp.263-269
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• 2001

The influences of background and environmental noise on coincidence detection are investigated with entangled photons produced by parametric down-conversion process. When the down-converted photons are mixed with thermal light, the coincidence rate did not vary with increasing noise level because the accidental coincidences are discriminated at the short resolving time window. The entangled photon source and the coincidence technique can effectively be used for a noise-free communication channel in the new field of quantum information transmission and processing. ssing.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.3
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• pp.221-226
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• 2008

A new two dimensional (2-D) analytical model for the Threshold Voltage on dual material surrounding gate (DMSG) MOSFETs is presented in this paper. The parabolic approximation technique is used to solve the 2-D Poisson equation with suitable boundary conditions. The simple and accurate analytical expression for the threshold voltage and sub-threshold swing is derived. It is seen that short channel effects (SCEs) in this structure is suppressed because of the perceivable step in the surface potential which screens the drain potential. We demonstrate that the proposed model exhibits significantly reduced SCEs, thus make it a more reliable device configuration for high speed wireless communication than the conventional single material surrounding gate (SMSG) MOSFETs.

• Proceedings of the KIEE Conference
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• 1987.07a
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• pp.469-472
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• 1987

The hot-carrier induced degradation in very short-channel MOSFET was studied systematically. Under the traditional DC stress conditions, the threshold voltage shift (${\Delta}Vt$) and the transconductance degradation (${\Delta}Gm$/(Gmo-${\Delta}Gm$)) were confirmed to depend exponentially on the stress time and the dependency between the two parameters was proved to be linear. And the degradation due to the DC stress across gate and drain was studied. As the AC dynamic process is more realistic in actual device operation, the effects of dynamic stresses were studied.

• Journal of Electrical Engineering and Technology
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• v.9 no.2
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• pp.655-661
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• 2014

In this paper, a new two dimensional (2D) analytical modeling and simulation for a surrounding gate tunnel field effect transistor (TFET) is proposed. The Parabolic approximation technique is used to solve the 2-D Poisson equation with suitable boundary conditions and analytical expressions for surface potential and electric field are derived. This electric field distribution is further used to calculate the tunneling generation rate and thus we numerically extract the tunneling current. The results show a significant improvement in on-current characteristics while short channel effects are greatly reduced. Effectiveness of the proposed model has been confirmed by comparing the analytical results with the TCAD simulation results.

• ETRI Journal
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• v.44 no.3
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• pp.491-503
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• 2022

Metal-oxide-semiconductor field-effect transistors (MOSFETs) are continuously scaling down in the nanoscale region to improve the functionality of integrated circuits. The scaling down of MOSFET devices causes short-channel effects in the nanoscale region. In nanoscale region, leakage current components are increasing, resulting in substantial power dissipation. Very large-scale integration designers are constantly exploring different effective methods of mitigating the power dissipation. In this study, a transistor-level input-controlled stacking (ICS) approach is proposed for minimizing significant power dissipation. A low-power ICS approach is extensively discussed to verify its importance in low-power applications. Circuit reliability is monitored for process and voltage and temperature variations. The ICS approach is designed and simulated using Cadence's tools and compared with existing low-power and high-speed techniques at a 22-nm technology node. The ICS approach decreases power dissipation by 84.95% at a cost of 5.89 times increase in propagation delay, and improves energy dissipation reliability by 82.54% compared with conventional circuit for a ring oscillator comprising 5-inverters.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.693-695
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• 2012

This paper have presented the breakdown voltage for double gate(DG) MOSFET. The analytical solution of Poisson's equation and Fulop's breakdown condition have been used to analyze for breakdown voltage. The double gate(DG) MOSFET as the device to be able to use until nano scale has the adventage to reduce the short channel effects. But we need the study for the breakdown voltage of DGMOSFET since the decrease of the breakdown voltage is unavoidable. To approximate with experimental values, we have used the Gaussian function as charge distribution for Poisson's equation, and the change of breakdown voltage has been observed for device geometry. Since this potential model has been verified in the previous papers, we have used this model to analyze the breakdown voltage. As a result to observe the breakdown voltage, the smaller channel length and the higher doping concentration become, the smaller the breakdown voltage becomes. Also we have observed the change od the breakdown voltage for gate oxide thickness and channel thickness.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.3
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• pp.575-580
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• 2015

Asymmetric double gate(DG) MOSFET is a novel transistor to be able to reduce the short channel effects. This paper has analyzed a off current for conduction path of asymmetric DGMOSFET. The conduction path is a average distance from top gate the movement of carrier in channel happens, and a factor to change for oxide thickness of asymmetric DGMOSFET to be able to fabricate differently top and bottom gate oxide thickness, and influenced on off current for top gate voltage. As the conduction path is obtained and off current is calculated for top gate voltage, it is analyzed how conduction path influences on off current with parameters of oxide thickness and channel length. The analytical potential distribution of series form is derived from Poisson's equation to obtain off current. As a result, off current is greatly changed for conduction path, and we know threshold voltage and subthreshold swing are changed for this reasons.

• Journal of the Korean Institute of Telematics and Electronics T
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• v.35T no.1
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• pp.7-13
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• 1998

The VLSI devices of submicron level trend to have a lowering of reliability because of hot carriers by two dimensional influences which are caused by short channel effects and which are not generated in a long channel devices. In order to minimize the two dimensional influences, much research has been made into various types of source/drain structures. MOS typed tunnel transistor with Schottky barrier junctions at source/drain, which has the advantages in fabrication process, downsizing and response speed, has been proposed. The experimental device was fabricated with p type silicon, and manifested the transistor action, showing the unsaturated output characteristics and the high transconductance comparing with that in field effect mode. The results of trial indicate for better performance as follows; high doped channel layer to lower the driving voltage, high resistivity substrate to reduce the leakage current from the substrate to drain.