• Journal of Institute of Control, Robotics and Systems
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• v.7 no.6
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• pp.540-549
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• 2001

An implementation method for chip-mounter simulator is proposed to improve the productivity and utility of electronic assembly lines. The simulator emulates the assembly sequence graphically to verify the chip mounter program in offline. It also presents functions of time estimation and productivity analysis considering the error probability. To increase the flexibility of simulator, stochastic petri nets are applied to modeling of the assembly sequence. The sequence model is then implemented as extendable classes by an object oriented language. The simulator is applied to a commercial chip mounter to verify the usefulness of the method proposed.