• Proceedings of the Korea Multimedia Society Conference
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• 2003.05b
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• pp.61-64
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• 2003

본 논문에서는 의사난수발생기로 사용할 수 있는 산술 시프트 레지스터(ASR. Arithmetic Shift Register)를 제안한다. 산술 시프트 레지스터는 GF(2ⁿ)상에서 0이 아닌 초기 값에 0 또는 1이 아닌 임의의 수를 곱하는 수열로 정의한다. 산술 시프트 레지스터의 주기는 2ⁿ-1로 최대 주기를 가진다. 또한 소프트웨어 및 하드웨어로 구현이 용이하다. 제안한 산술 시프트 레지스터는 종래의 선형귀환 시프트 레지스터와 같이 암호, 오류수정부호, 몬테카를로 적분, 데이터통신 둥 여러 분야에서 폭 넓게 사용될 수 있다.

• 한국초전도학회:학술대회논문집
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• v.9
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• pp.133-133
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• 1999

We have fabricated and tested a simple circuit of the rapid single-flux-quantum(RSFQ) four-stage shift register using a single layer high-T$_c$ superconducting (HTS) YBa$_2Cu_3O_{7-x}$ (YBCO) thin film structure with 9 step-edge Josephson junctions. The circuit includes two read superconducting quantum interference devices(SQUID) and four stages. To establish a robust HTS RSFQ device fabrication process, we have focussed the reproducible process of sharp and straight step-edge formation as well as the ratio of film thickness to step height t/h. The spread of step-edge junction parameters was measured from each13 junctions with t/h=l/3, l/2, and 2/3 at various temperatures. We have demonstrated the simplified operation of the shift register at 65 K..

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.6
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• pp.1150-1156
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• 2009

In this paper, we propose the gradual encryption method of image using LFSR(Linear Feedback Shift Register) and 2D CAT(Two-Dimensional Cellular Automata Transform). First, an LFSR is used to create a PN(pseudo noise) sequence, which is identical to the size of the original image. Then the created sequence goes through an XOR operation with the original image resulting to the first encrypted image. Next, the gateway value is set to produce a 2D CAT basis function.The created basis function multiplied with the first encrypted image produces the 2D CAT encrypted image which is the final output. Lastly, the stability analysis verifies that the proposed method holds a high encryption quality status.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.164-167
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• 2009

In this paper, we propose the image encryption using LFSR(Linear Feedback Shift Register) and 2D CAT(Two-Dimensional Cellular Automata Transform). First, a LFSR is used to create a PN(pseudo noise) sequence, which is identical to the size of the original image. Then, the created sequence goes through a XOR operation with the original image to convert the original image. Next, the gateway value is set to produce a 2D CAT basis function. Using the created basis function, multiplication is done with the converted original image to process 2D CAT image encipherment. Lastly, the stability analysis verifies that the proposed method holds a high encryption quality status.

• Journal of the Korea Society of Computer and Information
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• v.15 no.1
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• pp.13-21
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• 2010

IEEE 1149.1 test architecture was proposed to support the test of elements within the boards. It is a large serial shift register that uses the TDI pin as an input and the TDO pin as an output. Even though it performs the board level test perfectly, there is a problems of running system level test when the boards are equipped to the system. To test real time operation signal on test pin, output speed of serial shift register chain must be above double clock speed of shift register. In this paper, we designed a runtime test architecture and a runtime test procedure under running system environments to capture runtime signal at system clock rate. The suggested runtime test architecture are simulated by Altera Max+Plus 10.0. through the runtime test procedure. The simulation results show that operations of the suggested runtime test architecture are very accurate.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1495-1498
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• 1987

This paper described the design of register part, ROM and entire digital filter implementation by merging with ALU, control part last year. The register part consists of shift register, parallel load serial output register, multiplexer and selector, and we designed specially the 1024 memory cells ROM and decoder to decode the register data. Also, presented scaling algorithm to prevent the overflow.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1992.10a
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• pp.379-381
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• 1992

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.3
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• pp.77-85
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• 2002

A Research of binary random sequence generator that uses a linear shift register had been studied since the 1970s. These generators were used in stream cipher. In general, the binary random sequence generator consists of linear shift registers that generate sequences of maximum period and a nonlinear filter function or a nonlinear combination function to generate a sequence of high linear complexity. Therefore, To generate a sequence that have long period as well as high linear complexity becomes an important factor to estimate safety of stream cipher. Usually, the maximum period of the sequence generated by a linear feedback shift register with L resistors is less than or equal to $2^L$-1. In this paper, we propose new binary random sequence generator that consist of L registers and 2 sub-characteristic polynomials. According to an initial state vector, the least period of the sequence generated by the proposed generator is equal to or ions than it of the sequence created by the general linear feedback shift register, and its linear complexity is increased too.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.38 no.4
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• pp.18-26
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• 2001

In this paper, we propose an ATC(Automatic Transfer mode Controller) algorithm and an average-mode-change method for use in Gear shift PLL which can automatically change loop gain. The proposed ATC algorithm accurately detects proper timing or the mode change and has a very simpler structure - than the conventional lock detector algorithm often used in QPSK. And the proposed average mode change method can obtain low errors of estimated frequency offset by averaging the loop filter output of frequency component in shift register. These algorithms are also useful in designing ASIC, since these algorithms occupy small circuit area and are adaptable for high speed digital processing. We also present phase tracking performance of proposed Gear-shift PLL, which is composed of polarity decision PD, ATC and average mode change circuit, and analyze the results by examining constellation at each mode.

• Journal of Communications and Networks
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• v.13 no.1
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• pp.1-5
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• 2011

Feedback with carry shift registers (FCSRs) over 2-adic number would be suitable in hardware implementation, but the are not efficient in software implementation since their basic unit (the size of register clls) is 1-bit. In order to improve the efficiency we consider FCSRs over $2^{\ell}$-adic number (i.e., FCSRs with register cells of size ${\ell}$-bit) that produce ${\ell}$ bits at every clocking where ${\ell}$ will be taken as the size of normal words in modern CPUs (e.g., ${\ell}$ = 32). But, it is difficult to deal with the carry that happens when the size of summation results exceeds that of normal words. We may use long variables (declared with 'unsigned _int64' or 'unsigned long long') or conditional operators (such as 'if' statement) to handle the carry, but both the arithmetic operators over long variables and the conditional operators are not efficient comparing with simple arithmetic operators (such as shifts, maskings, xors, modular additions, etc.) over variables of size ${\ell}$-hit. In this paper, we propose some conditions for FCSRs over $2^{\ell}$-adic number which admit fast software implementations using only simple operators. Moreover, we give two implementation examples for the FCSRs. Our simulation result shows that the proposed methods are twice more efficient than usual methods using conditional operators.