• ETRI Journal
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• v.43 no.5
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• pp.900-908
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• 2021

This paper proposes thermometer-code latches having five and six transistors for unidirectional and bidirectional thermometer-code shift-registers, respectively. The proposed latches omit the set and reset transistors by changing from two supply voltage nodes to the set and reset signals in the cross-coupled inverter. They set or reset the data by changing the supply voltage to ground in either of two inverters. They reduce the number of transistors to five and six compared with the conventional thermometer-code latches having six and eight transistors, respectively. The proposed thermometer-code latches were simulated using a 65 nm complementary metal-oxide-semiconductor (CMOS) process. For comparison, the proposed and conventional latches are adapted to the 64 bit thermometer-code shift-registers. The proposed unidirectional and bidirectional shift-registers occupy 140 ㎛² and 197 ㎛², respectively. Their consumption powers are 4.6 ㎼ and 5.3 ㎼ at a 100 MHz clock frequency with the supply voltage of 1.2 V. They decrease the areas by 16% and 13% compared with the conventional thermometer-code shift-register.

• 한국초전도학회:학술대회논문집
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• v.9
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• pp.102-106
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• 1999

We have designed and fabricated a four-bit shift register circuit using YBCO bicrystal junctions and experimentally tested its operations by a computer-controlled digital measurement set-up. Laser ablated YBCO thin films with clean surface were used in this work. The circuit consists of the shift register and two read SQUIDs placed next to each sides of the shift register. The SQUIDs were inductively coupled to the nearby shift register stages. A probe equipped with high speed coax lines were used in this experiment. The major obstacle in testing the circuit was the interference between the read SQUIDs and we solved the problem by finding the correct operation points of the SQUIDs from the simultaneously measured modulation curves. Loaded Data("1" or "0") were successfully shifted from a stage to the next one by a controlled current pulse injected to the bias lines located between the stages and the data shifts were correctly monitored by the read SQUIDs

• ETRI Journal
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• v.36 no.2
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• pp.321-324
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• 2014

This letter describes a two-phase clock oxide thin-film transistor shift register that executes a robust operation over a wide threshold voltage range and clock coupling noises. The proposed circuit employs an additional Q generation block to avoid the clock coupling noise effects. A SMART-SPICE simulation shows that the stable shift register operation is established for the clock coupling noises and the threshold voltage variation from -4 V to 5 V at a line time of $5{\mu}s$. The magnitude of coupling noises on the Q(15) node and Qb(15) node of the 15th stage is respectively -12.6 dB and -26.1 dB at 100 kHz in the proposed circuit, compared to 6.8 dB and 10.9 dB in a conventional one. In addition, the estimated power consumption is 1.74 mW for the proposed 16-stage shift registers at $V_{TH}=-1.56V$, compared to 11.5 mW for the conventional circuits.

• Progress in Superconductivity
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• v.1 no.1
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• pp.31-35
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• 1999

We have fabricated and tested a simple circuit of the rapid single-flux-quantum(RSFQ) four-stage shift register using a single layer high-$T_c$ superconducting (HTS) $YBa_2Cu_3O_{7-x}$ (YBCO) thin film structure with 9 step-edge Josephson junctions. The circuit includes two read superconducting quantum interference devices(SQUID) and four stages. To establish a robust HTS RSFQ device fabrication process, we have focussed on the reproducible process of sharp and straight step-edge formation as well as the ratio of film thickness to step height, t/h. The spread of step-edge junction parameters was measured from each 13 junctions with t/h=1/3, 1/2, and 2/3 at various temperatures. We have demonstrated the simplified operation of the shift register at 65 K.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.1
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• pp.83-91
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• 1993

In the digital transmission system, cyclic redundancy check(CRC) code is widely used because it is easy to be implemented and has good performance in error detection. CRC code generator consists of several shift registers and modulo 2 adders. After manipulation of input data stream in the encoder, the remaining value of shift registers becomes CRC code. At the receiving side, error can be detected and corrected by CRC codes immediately transmitted after data stream. But, in the high speed system such as an A TM switch, it is difficult to implement the serial CRC encoder because of speed limitation of available semiconductor devices. In this paper, we propose the efficient parallel CRC encoder and syndrome calculator to solve the speed problem in implementing these functions using the existing semiconductor technology.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.2269-2270
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• 2008

Zigbee that is the wireless personal area networks communication technology for low power consumption is low-cost, low-power consumption, and small size and program code. From the present paper symbol and chip sequence of existing Zigbee module undergarment PN code generators which are a 1:1 mapping method it uses shift register and it plans the method which it proposes. The experimental result used Xilinx ISE and it measured synthesis and timing and power.

• Journal of applied mathematics & informatics
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• v.39 no.5_6
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• pp.859-882
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• 2021

In the proposed paper, a new algorithm based on Nonlinear Feedback Shift Register (NLFSR) and modified RC4A (Rivest Cipher 4A) cipher is introduced. NLFSR is used for image pixel scrambling while modified RC4A algorithm is used for pixel substitution. NLFSR used in this algorithm is of order 27 with maximum period 2^27-1 which was found using Field Programmable Gate Arrays (FPGA), a searching method. Modified RC4A algorithm is the modification of RC4A and is modified by introducing non-linear rotation operator in the Key Scheduling Algorithm (KSA) of RC4A cipher. Analysis of occlusion attack (up to 62.5% pixels), noise (salt and pepper, Poisson) attack and key sensitivity are performed to assess the concreteness of the proposed method. Also, some statistical and security analyses are evaluated on various images of different size to empirically assess the robustness of the proposed scheme.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.14 no.3
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• pp.235-239
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• 1989

A multiplier is proposed for computing multiplication of two arbitrary elements in the finite fields GF($2^m$), and the operation process is described step by step. The modified type of the circuit which is constructed with m-stage feedgack shift register, m-1 flip-flop, m AND gate, and m-input XOR gate is presented by referring to the conventional shift-register multiplier. At the end of mth shift, the shift-register multiplier stores the product of two elements of GF($2^m$); however the proposed circuit in this paper requires m-1 clock times from first input to first output. This circuit is simpler than cellulra-array or systolic multiplier and moreover it is faster than systolic multiplier.

• 한국초전도학회:학술대회논문집
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• v.11
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• pp.48-48
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• 2001

• Proceedings of the KIEE Conference
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• 1987.07a
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• pp.411-415
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• 1987

A $32{\times}33$ MOS-type area image sensor has been fabricated. The blooming current is reduced to 1/14 by forming +p photocell in P-well instead of a simple p-type substrate. A shallow n+ junction is made to improve the sensitivity of photodiode on short wavelength. Bootstrapping circuit technique is applied to obtain high speed dynamic shift register. The shift register operates at up to 10MHz for 7V clock.