• Asian-Australasian Journal of Animal Sciences
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• v.7 no.3
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• pp.303-316
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• 1994

Microbial digestion of feed in the rumen involves a sequential attack culminating in the formation of fermentation products and microbial cells that can be utilized by the host animal. Most feeds are protected by a cuticular layer which is in effect a microbial barrier that must be penetrated or circumvented for digestion to proceed. Microorganisms gain access to digestible inner plant tissues through damage to the cuticle, or via natural cell openings (e.g., stomata) and commence digestion from within the feed particles. Primary colonizing bacteria adhere to specific substrates, divide to form sister cells and the resultant microcolonies release soluble substrates which attract additional microorganisms to the digestion site. These newly attracted microorganisms associate with primary colonizers to form complex multi-species consortia. Within the consortia, microorganisms combine their metabolic activities to produce the diversity of enzymes required to digest complex substrates (e.g., cellulose, starch, protein) which comprise plant tissues. Feed characteristics that inhibit the microbial processes of penetration, colonization and consortia formation can have a profound effect on the rate and extent of feed digestion in the rumen. Strategies such as feed processing or plant breeding which are aimed at manipulating feed digestion must be based on an understanding of these basic microbial processes and their concerted roles in feed digestion in the rumen.

• Proceedings of the Korea Water Resources Association Conference
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• 1991.07a
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• pp.5-12
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• 1991

수자원 관련 연구 및 설계는 대부분 수문자료의 분석으로보터 출발하며, 따라서 수문자료의 효율적 관리 및 제공시스템의 필요성이 강조되어 왔다. 또한 설계회사 또는 학계, 연구소 등에서 수문자료의 분석시 퍼스날 컴퓨터를 이용하는 경우가 상당히 많으며, 단위 프로젝트에 필요한 비교적 적은 양 - 예를 들어 전국 중 특정 수계만을 대상으로 하는 경우 - 의 수문자료는 퍼스날 컴퓨터로도 처리가 가능하므로, 프로젝트 단위 수문자료의 검색, 출력 및 기본적 분석기능을 제공하는 퍼스날 컴퓨터용 수문데이타베이스의 개발 필요성이 제기되었다. PCHISS(Personal Computer Hydrological Information Support System)는 이러한 필요성에 의해 폭넓게 보급, 사용되고 있는 퍼스날 컴퓨터 - MS-DOS로 운영되는 IBM 호환 16비트 AT 또는 XT - 를 대상으로 상기한 수문자료의 검색, 출력 및 기본적 분석기능과 관측소 정보의 출력기능을 제공하도록 개발되었다. 개발에 사용된 언어는 C언어이며, C언어 프로그램에 의해 색인화된 자료처리기능을 제공하는 C-ISAM(C-Indexed Sequential Access Method)이라는 라이브러리를 사용하였다. 개발된 수문데이타베이스는 반복되는 수문자료의 검색, 출력 및 분석업무의 효율성 제고를 기할 수 있으며, 퍼스날 컴퓨터 및 보조기억장치를 포함한 주변장치의 성능이 계속 향상되고, 반면 가격은 상대적으로 낮추어지고 있으므로 프로젝트 단위의 수문자료관리시스템의 역할을 충분히 수행할 수 있을 것으로 기대된다.

• Smart Structures and Systems
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• v.26 no.4
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• pp.419-433
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• 2020

Investigation of structural integrity has been a critical issue in the field of civil engineering for years. Visual inspection is one of the most available methods to explore deteriorative components in structures. Still, this method is not applicable to invisible damage of structures. Alternatively, system identification methods are capable of tracking modal properties of structures over time. The deviation of these dynamic properties can serve as indicators to access structural integrity. In this study, a modal tracking technique using frequency-domain system identification from seismic responses of structures is proposed. The method first segments the measured signals into overlapped sequential portions and then establishes multiple Hankel matrices. Each Hankel matrix is then converted to the frequency domain, and a temporal-average frequency-domain Hankel matrix can be calculated. This study also proposes the frequency band selection that can divide the frequency-domain Hankel matrix into several portions in accordance with referenced natural frequencies. Once these referenced natural frequencies are unavailable, the first few right singular vectors by the singular value decomposition can offer these references. Finally, the frequency-domain stochastic subspace identification tracks the natural frequencies and mode shapes of structures through quick stabilization diagrams. To evaluate performance of the proposed method, a numerical study is carried out. Moreover, the long-term monitoring strong motion records at a specific site are exploited to assess the tracking performance. As seen in results, the proposed method is capable of tracking modal properties through seismic responses of structures.

• English Language & Literature Teaching
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• v.11 no.2
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• pp.19-34
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• 2005

Hypertext raises question to general assumptions about our conventional conceptions of education. In this essay, three kinds of learning-models are presented by the application of "writing" hypertext literature to the English education of the elementary school. These models, which I call the "scene-centered" system, give knowledge to learners in non-linear, non-sequential structure. The term "scene" is a single concept or idea composed of a single sub-text, which is to be made by the group of students. This system is focused on the collaborative composition of students. Students, by generating sub-texts and connecting texts, perform the educational activities to expand the source text. The "scene-centered" system is, to put it into a Barte's term, a "writerly text." But in order to "write," "reading" should be accompanied. So, this system is a learning model in which writing and reading are carried on simultaneously. In all the process, students play a role of multi-user, with three access rights: read, write, and annotate. So, students making use of hypertext systems will act as reader-authors. And teachers will take the new role in collaborative writing environment. No longer the central authoritarian evaluator, they will become consultants, co-writers, coaches of their students.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.12C
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• pp.1642-1651
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• 2004

Advance of internet access technology requires more internet bandwidth and high-speed packet processing. IP address lookups in routers are essential elements which should be performed in real time for packets arriving tens-of-million packets per second. In this paper, we proposed a new architecture for efficient IP address lookup. The proposed scheme produces multiple balanced trees stored into a single SRAM. The proposed scheme performs sequential binary searches on multiple trees. Performance evaluation results show that p개posed architecture requires 301.7KByte SRAM to store about 40,000 prefix samples, and an address lookup is achieved by 11.3 memory accesses in average.

• Journal of Internet Technology
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• v.20 no.3
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• pp.827-838
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• 2019

The recent evolution of mobile devices and services have resulted in such plethora of mobile applications (apps) that users have difficulty finding the ones they wish to use in a given moment. We design an app recommendation system which predicts the app to be executed with high accuracy so that users are able to access their next app conveniently and quickly. We introduce the App-Usage Tracking Feature (ATF), a simple but powerful feature for predicting next app launches, which characterizes each app use from the sequence of previously used apps. In addition, our method can be implemented without compromising the user privacy since it is solely trained on the target user's mobile usage data and it can be conveniently implemented in the individual mobile device because of its less computation-intensive behavior. We provide a comprehensive empirical analysis of the performance and characteristics of our proposed method on real-world mobile usage data. We also demonstrate that our system can accurately predict the next app launches and outperforms the baseline methods such as the most frequently used apps (MFU) and the most recently used apps (MRU).

• Journal of Korea Multimedia Society
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• v.12 no.10
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• pp.1374-1385
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• 2009

Recently, advances in speed of the CPU have for out-paced advances in memory speed. Main-memory access is increasingly a performance bottleneck for main-memory database systems. To reduce memory access speed, cache memory have incorporated in the memory subsystem. However cache memories can reduce the memory speed only when the requested data is found in the cache. We propose a new cache sensitive T-tree index structure called as $CST^*$-tree for range query search. The $CST^*$-tree reduces the number of cache miss occurrences by loading the reduced internal nodes that do not have index entries. And it supports the sequential access of index entries for range query by connecting adjacent terminal nodes and internal index nodes. For performance evaluation, we have developed a cost model, and compared our $CST^*$-tree with existing CST-tree, that is the conventional cache sensitive T-tree, and $T^*$-tree, that is conventional the range query search T -tree, by using the cost model. The results indicate that cache miss occurrence of $CST^*$-tree is decreased by 20~30% over that of CST-tree in a single value search, and it is decreased by 10~20% over that of $T^*$-tree in a range query search.

• Journal of KIISE:Databases
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• v.35 no.1
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• pp.17-28
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• 2008

Recently, main memory access is a performance bottleneck for many computer applications. Cache memory is introduced in order to reduce memory access latency. However, it is possible for cache memory to reduce memory access latency, when desired data are located on cache. EST tree is proposed to solve this problem by improving T tree. However, when doing a range search, EST tree has to search unnecessary nodes. Therefore, this paper proposes $CST^+$ tree which has the merit of CST tree and is possible to do a range search by linking data nodes with linked lists. By experiments, we show that $CST^+$ is $4{\sim}10$ times as fast as CST and $CSB^+$. In addition, rebuilding an index Is an essential step for the database recovery from system failure. In this paper, we propose a fast tree index rebuilding algorithm called MaxPL. MaxPL has no node-split overhead and employs a parallelism for reading the data records and inserting the keys into the index. We show that MaxPL is $2{\sim}11$ times as fast as sequential insert and batch insert.

• The KIPS Transactions:PartA
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• v.18A no.4
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• pp.135-142
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• 2011

This research is to design an effective buffer structure and its management for flash memory based high performance SSDs (Solid State Disks). Specifically conventional SSDs tend to show asymmetrical performance in read and /write operations, in addition to a limited number of erase operations. To minimize the number of erase operations and write latency, the degree of interleaving levels over multiple flash memory chips should be maximized. Thus, to increase the interleaving effect, an effective buffer structure is proposed for the SSD with a hybrid address mapping scheme and super-block management. The proposed buffer operation is designed to provide performance improvement and enhanced flash memory life cycle. Also its management is based on a new selection scheme to determine random and sequential accesses, depending on execution characteristics, and a method to enhance the size of sequential access unit by aggressive merging. Experiments show that a newly developed mapping table under the MBA is more efficient than the basic simple management in terms of maintenance and performance. The overall performance is increased by around 35% in comparison with the basic simple management.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.12
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• pp.2783-2790
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• 2010

In this paper, we first review LDPC codes in general and a belief propagation algorithm that works in logarithm domain. LDPC codes, which is chosen 802.11n for wireless local access network(WLAN) standard, require a large number of computation due to large size of coded block and iteration. Therefore, we presented three kinds of low computational algorithms for LDPC codes. First, sequential decoding with partial group is proposed. It has the same H/W complexity, and fewer number of iterations are required with the same performance in comparison with conventional decoder algorithm. Secondly, we have apply early stop algorithm. This method reduces number of unnecessary iterations. Third, early detection method for reducing the computational complexity is proposed. Using a confidence criterion, some bit nodes and check node edges are detected early on during decoding. Through the simulation, we knew that the iteration number are reduced by half using subset algorithm and early stop algorithm is reduced more than one iteration and computational complexity of early detected method is about 30% offs in case of check node update, 94% offs in case of check node update compared to conventional scheme. The LDPC decoder have been implemented in Xilinx System Generator and targeted to a Xilinx Virtx5-xc5vlx155t FPGA. When three algorithms are used, amount of device is about 45% off and the decoding speed is about two times faster than convectional scheme.