• 대한전기학회논문지:전력기술부문A
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• 제48권12호
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• pp.1554-1563
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• 1999

This paper presents the design of high speed processor for a sequence logic control using field programmable gate array(FPGA). The sequence logic controller is widely used for automating a variety of industrial plants. The FPGA designed by VHDL consists of program and data memory interface block, input and output block, instruction fetch and decoder block, register and ALU block, program counter block, debug control block respectively. Dedicated clock inputs in the FPGA were used for high speed execution, and also the program memory was separated from the data memory for high speed execution of the sequence instructions at 40 MHz clock. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 16 bits or 32 bits respectively. And the real time debug operation was implemented for easy debugging the designed processor. This FPGA was synthesized by pASIC 2 SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to sequence control system with inputs and outputs of 256 points. The designed processor for the sequence logic was compared with the control system using the DSP(TM320C32-40MHz) and conventional PLC system. The designed processor for the sequence logic showed good performance.

• 대한전기학회논문지
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• 제40권8호
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• pp.836-844
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• 1991

PLC(programmable logic controller) system is widely used for the control of factory. PLC system receives ladder diagram which is drawn by the user to implement hardware logic, converts the ladder diagram into sequence program which is executable in the PLC system, and executes the sequence program indefinitely unless user breaks. The sequence program processes the data of on/off signal, and endures 1 scan delay and missing of pulse-type signal shorter than a scan time. So, data dependency doesn't exist. By applying theis characteristics to multiprocessor architecture, we design parellel PLC functionally and evaluate performance upgrade. Parallel PLC consists of central processing module, N general processing unit, and a shared memory by master-slave type. Each module executes allocated sequence program by the control of central processing module. We can expect performance upgrade by parallel processing, and reliability by relocation of sequence program when error occurs in processing module.

• 한국통신학회논문지
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• 제13권6호
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• pp.370-479
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• 1988

GRAFCET로 기술된 병렬 시퀀스를 갖는 순서논리 시스템을 실현하는 microprogrammable sequential controller의 실현방법을 제시했다. 제시된 콘트롤러는 처리속도 및 가변성의 향상과 ROM 프로그래밍을 용이하게 할 수 있도록 구성되었다. 또한 병렬 시퀀스를 처리할 수 있으므로 제어시스템의 효율을 향상시킬 수 있다. 따라서 많은 입출력 변수를 갖는 industial process나 빠른 처리속도를 요하는 power electronic converter등의 콘트롤러 실현에 적합하다.

• 한국통신학회논문지
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• 제13권6호
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• pp.470-470
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• 1988

GRAFCET로 기술된 병렬 시퀀스를 갖는 순서논리 시스템을 실현하는 microprogrammable sequential controller의 실현방법을 제시했다. 제시된 콘트롤러는 처리속도 및 가변성의 향상과 ROM 프로그래밍을 용이하게 할 수 있도록 구성되었다. 또한 병렬 시퀀스를 처리할 수 있으므로 제어시스템의 효율을 향상시킬 수 있다. 따라서 많은 입출력 변수를 갖는 industial process나 빠른 처리속도를 요하는 power electronic converter등의 콘트롤러 실현에 적합하다.

• 융합신호처리학회 학술대회논문집
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• 한국신호처리시스템학회 2000년도 추계종합학술대회논문집
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• pp.209-212
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• 2000

본 논문에서는 AGV(Automatic Guided Vehicle)를 제어하기 위한 hard-wired 제어기를 설계하였고, CPLD(Complex Programmable Logic Device)를 이용하여 구현하였다. 제안된 제어기는 자율주행을 위한 유도장치 제어기, 모터 제어장치, 입출력 sequence 제어기 등을 포함하고 있다. 마이크로프로세서에 의해 구현된 기존방식에 비해 hard-wired 제어방식을 사용하므로 복잡한 프로그램 과정을 줄일 수 있다. 또한 메모리, 조합논리, 순서논리 회로를 쉽게 추가할 수 있어 제품의 개발시간 단축, 제품 크기 축소, 난이도 등에서 발생되는 총 제작비용 등을 감소시킬 수 있다. 제어기는 VHDL을 이용하여 동작적 기술 방법으로 설계되었으며, Altera사의 MAX＋Plus II를 사용하여 합성하였고, EPF10K10LC84-4 디바이스로 구현하여 AGY 모형(Line-tracer)에 적용시켜 동작을 확인하였다.

• 전기전자학회논문지
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• 제2권2호
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• pp.299-308
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• 1998

본 논문에서는 신뢰할 수 있는 SRM 구동시스템과 기존의 PI제어기에 4개의 규칙으로 이루어진 FLM(Fuzzy Logic Modifier)를 제안하였다. 저가격 원칩 마이크로컨트롤러인 인텔사의 i80C196KC는 속도 제어기와 초기 기동을 포함한 SRM 구동 컨트롤러를 설계하기 위해 사용되었다. 폐루프 시스템에 안정된 효과를 보이는 FLM을 Pl 제어기에 추가함으로써 부적절하게 설정된 PI 제어기의 이득값에 대해 강인한 제어성능을 보인다. 시뮬레이션 및 실험결과는 6/4극 SRM에 대해 제안된 제어 방식이 우수함을 보여준다.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1997년도 한국자동제어학술회의논문집; 한국전력공사 서울연수원; 17-18 Oct. 1997
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• pp.752-755
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• 1997

In this paper, a scheduling algorithm is proposed for a programmable logic controller(PLC) with remote I/Os, assuming the multi-tasking facilities. Since sequence programs are executed on the application processor and I/O data are transmitted by the network processor concurrently, the proposed algorithm schedules the data transmission as well as the sequence program execution. The suggested algorithm guarantees the bounded WCRT(worst case response time), which is the one third of the WCRT in the absence of scheduling. Computer simulation shows that the algorithm can be easily applied to a real PLC without critical constraints on utilization of resources and inter-relation among tasks.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2009년도 정보 및 제어 심포지움 논문집
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• pp.305-307
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• 2009

When we design the control system used Programmable Logic Controller(PLC), we program the main algorithm by Ladder Diagram(LD) among the standard language. We can substitute the select sequence function by the unique sequence. We can implement this function by the delay time. Therefore this thesis show the select sequence function by the unique sequence and we confirmed its feasibility through actual example.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1997년도 한국자동제어학술회의논문집; 한국전력공사 서울연수원; 17-18 Oct. 1997
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• pp.585-588
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• 1997

This paper presents a construction method of logic-based switching control system which operates in widely changing environments. The logic-based switching controller is composed of a family of candidate controllers together with a supervisor. The system does not require any identification schemes of environments. Switching from one candidate controller to another is carried out based on monitoring the output of the system. The basic ideas of adaptation are as follows: (1)each candidate controller is prepared for each environment in advance; (2)the supervisor applies a sequence of speculative controls to a plant with candidate controllers just after the control has started and just after the change of the environment has been detected. It is important that each candidate controller can keep the system stable during a sequence of speculative controls, and the most appropriate candidate controller for the environment to which the system is exposed can be selected before the last speculative control is ended. An application to an antiskid braking system clarifies the effectiveness of the proposed method.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1987년도 한국자동제어학술회의논문집; 한국과학기술대학, 충남; 16-17 Oct. 1987
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• pp.407-412
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• 1987

A large scale programmable controller is developed which adopts a multiprocessor structure. The developed programmable controller consists of the programmer, the system controller, and the input-output unit. The structure and characteristics of the system controller will be described. The PC has a special hardware scheme to solve the Boolean logic instructions of the sequence control programs. The multiprocessor structure and the special hardware enables, the real time operation and the high speed scanning which is prerequisite to the large scale, programmable controller even for many I/O points.