• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2007년도 추계학술대회 논문집
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• pp.232-232
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• 2007

• 한국재료학회지
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• 제15권3호
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• pp.183-188
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• 2005

It was studied in this article how the flexural strength of bare silicon chips is influenced by adopting dual wafer back-lapping process. The experimental results showed that an additional finishing process after the conventional grinding process improves the flexural strength of bare chips by more than 2-fold. In particular, this work showed that the proper removal of the grinding marks$(Ra=0.1\;{\mu}m)$existing on the wafer back-surface resulting from the grinding process significantly contiributes to the enhancement of chip strength.

• 한국정밀공학회지
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• 제19권2호
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• pp.187-194
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• 2002

For the fine grinding process development of semiconductor monocrystalline silicon, wheel rotational speed, chuck rotational speed, feed rate and hysteresis force were controlled. Magic mirror system was used for grinding wheel pattern analysis. Curvature of wheel pattern was measured by fitting equation. The modeling of surface wheel pattern was related to wheel and chuck rotational speed. The calculated curvature of the model was well matched with the measured curvature. The statistical analysis indicated wheel and chuck rotational speed were significantly effective on.

• 대한금속재료학회지
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• 제49권9호
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• pp.726-731
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• 2011

The present work shows how the flexural displacement-induced fracture strength of silicon devices, whose back surfaces have wafer grinding-induced scratch marks, depends on the crystallographic orientation. Experimental results indicate that silicon devices with scratch marks parallel to their lateral direction (i.e. reference axis in this work) are very susceptible to flexural fracture, as compared to devices with marks which deviated from the direction. The 3-point bending test shows that the fracture strength of silicon devices having marks which are oriented away from the reference axis is 2.6 times higher than that of devices with marks parallel to the axis. It was particularly interesting to see that silicon devices with identical preferred marks even reveal different fracture strengths, depending on whether the marks are involved in specific crystal planes such as {111} or {011}, called cleavage planes. This work demonstrates that silicon devices with the reference axis-aligned scratch marks not existing on such cleavage planes can have higher fracture strength approximately 20% higher than those existing on the planes.

• 한국재료학회지
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• 제19권5호
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• pp.288-292
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• 2009

This article shows various factors that influence the thermal-cycling reliability of semiconductor devices utilizing the lead-on-chip (LOC) die attach technique. This work details how the modification of LOC package design as well as the back-grinding and dicing process of semiconductor wafers affect passivation reliability. This work shows that the design of an adhesion tape rather than a plastic package body can play a more important role in determining the passivation reliability. This is due to the fact that the thermal-expansion coefficient of the tape is larger than that of the plastic package body. Present tests also indicate that the ceramic fillers embedded in the plastic package body for mechanical strengthening are not helpful for the improvement of the passivation reliability. Even though the fillers can reduce the thermal-expansion of the plastic package body, microscopic examinations show that they can cause direct damage to the passivation layer. Furthermore, experimental results also illustrate that sawing-induced chipping resulting from the separation of a semiconductor wafer into individual devices might develop into passivation cracks during thermal-cycling. Thus, the proper design of the adhesion tape and the prevention of the sawing-induced chipping should be considered to enhance the passivation reliability in the semiconductor devices using the LOC die attach technique.