• Journal of the Semiconductor & Display Technology
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• v.19 no.3
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• pp.12-18
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• 2020

In semiconductor manufacturing, defect detection is critical to maintain high yield. Currently, computer vision systems used in semiconductor photo lithography still have adopt to digital image processing algorithm, which often occur inspection faults due to sensitivity to external environment. Thus, we intend to handle this problem by means of using Mask R-CNN instead of digital image processing algorithm. Additionally, Mask R-CNN can be trained with image dataset pre-processed by means of the specific designed digital image filter to extract the enhanced feature map of Convolutional Neural Network (CNN). Our approach converged advantage of digital image processing and instance segmentation with deep learning yields more efficient semiconductor photo lithography inspection system than conventional system.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.1240-1243
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• 2004

Multi-Valued Image Entropy Coding (MVIEC) is a new class of joint source channel coding, which reduces both input-width (1/4) and average current (0.36-1.3) for LCD source drivers. This paper describes the detail results on MVIEC for several image sets in order to verify the practical performance.

• Korean Journal of Optics and Photonics
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• v.34 no.2
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• pp.61-65
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• 2023

This paper studies a method of applying pre-distortion to the image mask of the gobo illumination optical system to correct an irradiated image and irradiate a clear image. In the case of the gobo illumination optical system, since it is generally irradiated with a tilt, distortion in the upper and lower directions occurs severely in the image. To solve this problem, the correction coordinates of the image were derived using a proportional equation, and the distortion was corrected by applying them to the image mask. As a result, it was confirmed that the distortion was reduced by 64.5% compared to the case of using the existing image mask.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1991.11a
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• pp.87-94
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• 1991

This Paper is to aim the microdefect evaluation of semiconductor Package into a quantitative from NDI's image processing of ultrasonic wave. Accordingly, for the detection of delamination between the Joining condition of boundary microdefect of semiconductor packaga the result from sampling original image, histogramming, binary image or image processing of multinumerloal value is such as the follows. ([) The least limitation from the microdefect detection of the semiconductor package by surveying high ultrasonic wave seems to be about 0.8 $\mu\textrm{m}$ in degree. (2) A result of applying the image processing of multinumerical value to the semiconductor package it was possible to devide the Category into the effectiveness.

• Journal of the Semiconductor & Display Technology
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• v.19 no.4
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• pp.71-76
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• 2020

In this paper, we propose a super-resolution method that reconstructs compressed low-resolution images into high-resolution images. We propose a CNN model with a small number of parameters, and even if quantization is applied to the proposed model, super-resolution can be implemented without deteriorating the image quality. To further improve the quality of the compressed low-resolution image, a new degradation model was proposed instead of the existing bicubic degradation model. The proposed degradation model is used only in the training process and can be applied by changing only the parameter values to the original CNN model. In the super-resolution image applying the proposed degradation model, visual artifacts caused by image compression were effectively removed. As a result, our proposed method generates higher PSNR values at compressed images and shows better visual quality, compared to conventional CNN-based SR methods.

• Journal of the Semiconductor & Display Technology
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• v.22 no.4
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• pp.108-112
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• 2023

Precision manufacturing technology is rapidly developing due to the extreme miniaturization of semiconductor processes to comply with Moore's Law. Accurate and precise alignment, which is one of the key elements of the semiconductor pre-process and post-process, is very important in the semiconductor process. The center detection of wafer align marks plays a key role in improving yield by reducing defects and research on accurate detection methods for this is necessary. Methods for accurate alignment using traditional image sensors can cause problems due to changes in image brightness and noise. To solve this problem, engineers must go directly into the line and perform maintenance work. This paper emphasizes that the development of AI technology can provide innovative solutions in the semiconductor process as high-resolution image and image processing technology also develops. This study proposes a new wafer center detection method through variable thresholding. And this study introduces a method for detecting the center that is less sensitive to the brightness of LEDs by utilizing a high-performance object detection model such as YOLOv8 without relying on existing algorithms. Through this, we aim to enable precise wafer focus detection using artificial intelligence.

• International Journal of Precision Engineering and Manufacturing
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• v.5 no.3
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• pp.11-18
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• 2004

In this paper, the classification of artificial defects in semiconductor packages is studied by using pattern recognition technology. For this purpose, the pattern recognition algorithm includes the user made MATLAB code. And preprocess is made of the image process and self-organizing map, which is the input of the back-propagation neural network and the dimensionality reduction method, The image process steps are data acquisition, equalization, binary and edge detection. Image process and self-organizing map are compared to the preprocess method. Also the pattern recognition technology is applied to classify two kinds of defects in semiconductor packages: cracks and delaminations.

• Journal of the Semiconductor & Display Technology
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• v.10 no.3
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• pp.89-94
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• 2011

The image identification methodology associates an image with a unique identifiable representation. Whenever the methodology regenerates an identifier for the same image, moreover, the newly created identifier needs to be consistent in terms of representation value. In this paper, we discuss a methodology for image identifier generation utilizing luminance correlation. We furthermore propose a method for performance enhancement of the image identifier generation. We also demonstrate the experimental evaluations for uniqueness and similarity analysis and performance improvement that have shown favorable results.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.149-152
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• 2004

A new joint source channel coding reduces both input-width and average current consumption to transmit image data to LCD source drivers. As a source coding, it is based on entropy coding of differential pulse code modulation scheme, especially using median edge detector of image predictor. As a channel coding, it is not a simple pulse amplitude modulation, but linked by source entropy to reduce average amplitude. Simulation results show 1/4 width is achievable by 16-valued transmission with keeping conventional current consumption (0.36 to 1.3).

• Journal of Sensor Science and Technology
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• v.30 no.5
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• pp.295-299
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• 2021

In this study, we present a complementary metal-oxide-semiconductor (CMOS) binary image sensor. It can shoot an object rotating at a high-speed by using a gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector. The GBT PMOSFET-type photodetector amplifies the photocurrent generated by light. Therefore, it is more sensitive than a standard N+/P-substrate photodetector. A binary operation is installed in a GBT PMOSFET-type photodetector with high-sensitivity characteristics, and the high-speed operation is verified by the output image. The binary operations circuit comprise a comparator and memory of 1- bit. Thus, the binary CMOS image sensor does not require an additional analog-to-digital converter. The binary CMOS image sensor is manufactured using a standard CMOS process, and its high- speed operation is verified experimentally.