• Journal of the Semiconductor & Display Technology
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• v.11 no.2
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• pp.85-91
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• 2012

In this paper, the large data processing and suitable FAT32 file system for industrial system using a PLC and CF memory was implemented. Most of PLC can't save the large data in user data memory. So it's required to the external devices of CF memory or NAND flash memory. The CF memory is used in order to save the large data of PLC system. The file system using the CF memory is NTFS, FAT, and FAT32 system to configure in various ways. Typically, the file system which is widely used in industrial data storage has been implemented as modified FAT32. The conventional FAT 32 file system was not possible for multiple writing and high speed data accessing. The proposed file system was implemented by the large data processing module can be handled that the files are copied at the 40 bytes for 1msec speed logging and creating 8 files at the same time. In a sudden power failure, high reliability was obtained that the problem was solved using a power fail monitor and the non-volatile random-access memory (NVSRAM). The implemented large data processing system was applied the modified file system as FAT32 and the good performance and high reliability was showed.

• Journal of the Korean Society of Safety
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• v.16 no.2
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• pp.57-62
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• 2001

In order to analyze the mechanism of semiconductor device damages by ESD, this paper adopts a new charged-device model(CDM), field-induced charged nudel(FCDM), simulator that is suitable for rapid routine testing of semiconductor devices and provides a fast and inexpensive test that faithfully represents ESD hazards in plants. The high voltage applied to the device under test is raised by the fie]d of non-contacting electrodes in the FCDM simulator. which avoids premature device stressing and permits a faster test cycle. Discharge current md time are measured and calculated The FCDM simulator places the device at a huh voltage without transferring charge to it, by using a non-contacting electrode. The only charge transfer in the FCMD simulator happens during the discharge. This paper examine the field charging mechanism, measure device thresholds, and analyze failure modes. The FCDM simulator provides a Int and inexpensive test that faithfully represents factory ESD hazards. The damaged devices obtained in the simulator are analyzed and evaluated by SEM Also the results in this paper can be used for to prevent semiconductor devices from ESD hazards.

• Korean Journal of Metals and Materials
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• v.46 no.5
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• pp.310-314
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• 2008

Electromigration test of flip chip solder bump is performed at $140^{\circ}C$ C and $4.6{\times}10^4A/cm^2$ conditions in order to compare electromigration with thermomigration behaviors by using electroplated Sn-3.5Ag solder bump with Cu under-bump-metallurgy. As a result of measuring resistance with stressing time, failure mechanism of solder bump was evaluated to have four steps by the fail time. Discrete steps of resistance change during electromigration test are directly compared with microstructural evolution of cross-sectioned solder bump at each step. Thermal gradient in solder bump is very high and the contribution of thermomigration to atomic flux is comparable with pure electromigration effect.

• Journal of the Korean Society of Safety
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• v.12 no.4
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• pp.161-168
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• 1997

Most plants producing semiconductors use a lot of chemicals, hazardous materials, and explosive gases. Though those materials are hazardous too much, some works still have to be done manually by human workers. However, according to a historical survey, more than half industrial accidents of those plants resulted from human errors or malfunctions. Thus, this research aimed 1) to diagnose shifting hazardous materials of semiconductor plants, 2) to estimate failure probability of human workers through human reliability analysis, and 3) to find out the tasks on which educational emphasis should be put. Through personal interview and visiting working spots, shifting tasks were analyzed, and modelled into a 24-step work, and after that, THERP and ETA was applied. During the shifting work, estimated human failure probability under the assumption of independency, 2.3004E-05, underestimated that probability 8. l008E-05 which could be calculated under the assumption of dependency. And this analysis showed that gas leakage from an old cylinder occupies 78.27% in the case of independent failures whereas gas leakage from a new cylinder occupies 75.06% in the case of dependent failures. So it was concluded that dependency assumption may gloss real situations. In addition, confirming gauge of regulators and closing valves turned out to be the most important tasks than purge tasks.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.09a
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• pp.79-94
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• 2002

Root cause -Thermal expansion coefficient mismatch -Tape warpage -Initial die crack (die roughness) Guideline for failure prevention -Optimized tape/Substrate design for minimizing the warpage -Fine surface of die backside Root cause -Thermal expansion coefficient mismatch - Repetitive bending of a signal trace during TC cycle - Solder mask damage Guideline for failure prevention - Increase of trace width - Don't make signal trace passing the die edge - Proper material selection with thick substrate core Root cause -Thermal expansion coefficient mismatch -Creep deformation of solder joint(shear/normal) -Material degradation Guideline for failure Prevention -Increase of solder ball size -Proper selection of the PCB/Substrate thickness -Optimal design of the ball array -Solder mask opening type : NSMD -In some case, LGA type is better

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.2
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• pp.208-213
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• 2008

In order to assess the reliability of the electronics control unit for vehicles, accelerated life test model and procedure are developed. By using this method, failure mechanism and life distribution are analyzed. The main results are as follows : i) the main failure mechanism is degradation failure that is, junction destruction of a semiconductor resin by high temperature. ii) the life distribution of the electronics control unit for vehicles is fitted well to Weibull life distribution and the accelerated life model of that is fitted well to Arrhenius model. iii) at the result of the life distribution, accelerated life test method is developed, and test time for life assessment will be shortened by 5,000 hours by this test method.

• Proceedings of the KIEE Conference
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• 2000.07c
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• pp.1566-1568
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• 2000

This study refers to the crosslinked characteristics of XLPE cables by aging. The cable failure brings about an enormous loss of power supply and the immense expense for cable replacement. These characterization techniques can be used for identifying a cause of failure and for improving a quality of equipments Also, these play an important role in the detection of premature failure. In order to maintain a cable reliability, quality control is needed strictly. It can be possible to estimate a residual lifetime of power cable using characterization techniques.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.28 no.6
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• pp.360-364
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• 2015

Electronic systems based on solid state devices have changed to be more complicated and miniaturized as the electronic systems developed. If the electronic systems are exposed to HPEM (high power electromagnetics), the systems will be destroyed by the coupling effects of electromagnetic waves. Because the HPEM has fast rise time and high voltage of the pulse, the semiconductors are vulnerable to external stress factor such as the coupled electromagnetic pulse. Therefore, we will discuss about malfunction behavior and DFR (destruction failure rate) of the semiconductor caused by amplitude and repetition rate of the pulse. For this experiment, the pulses were injected into the pins of general purpose IC due to the fact that pulse injection test enables the phenomenon after the HPEM is coupled to power cables. These pulses were produced by pulse generator and their characteristics are 2.1 [ns] of pulse width, 1.1 [ns] of pulse rise time and 30, 60, 120 [Hz] of pulse repetition rate. The injected pulses have changed frequency, period and duty ratio of output generated by Timer IC. Also, as the pulse repetition rate increases the breakdown threshold point of the timer IC was reduced.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.39 no.2
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• pp.1-10
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• 2016

In this paper, we present a new way to derive the mean cycle time of the G/G/m failure prone queue when the loading of the system approaches to zero. The loading is the relative ratio of the arrival rate to the service rate multiplied by the number of servers. The system with low loading means the busy fraction of the system is low. The queueing system with low loading can be found in the semiconductor manufacturing process. Cluster tools in semiconductor manufacturing need a setup whenever the types of two successive lots are different. To setup a cluster tool, all wafers of preceding lot should be removed. Then, the waiting time of the next lot is zero excluding the setup time. This kind of situation can be regarded as the system with low loading. By employing absorbing Markov chain model and renewal theory, we propose a new way to derive the exact mean cycle time. In addition, using the proposed method, we present the cycle times of other types of queueing systems. For a queueing model with phase type service time distribution, we can obtain a two dimensional Markov chain model, which leads us to calculate the exact cycle time. The results also can be applied to a queueing model with batch arrivals. Our results can be employed to test the accuracy of existing or newly developed approximation methods. Furthermore, we provide intuitive interpretations to the results regarding the expected waiting time. The intuitive interpretations can be used to understand logically the characteristics of systems with low loading.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.208-222
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• 2015

For the performance-efficient integration of IPs on an SoC utilizing heterochronous multi-clock domains, we propose a synchronization scheme that causes low latency overhead when data are crossing clock boundaries. The proposed synchronization scheme is composed of a clock predictor and a synchronizer. The clock predictor of a sender clock domain produces a predicted clock that is used in a receiver clock domain to detect possible synchronization failures in advance. When the possible synchronization failures are detected, a synchronizer at the receiver delays data-capture times to avoid the possible synchronization failures. From the simulation of the proposed scheme through SPICE modeling using a Chartered $0.18{\mu}m$ CMOS process, we verified the functionalities and timing behavior of the clock predictor and the synchronizer. The simulation results show that the clock predictor produces a predicted clock before a synchronization failure, and the synchronizer samples data correctly using the predicted clock.