• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.4
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• pp.14-23
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• 2011

In this paper, a 7-bit 2GSPS folding/interpolation A/D Converter(ADC) with a Self-Calibrated Vector Generator is proposed. The ADC structure is based on a folding/interpolation architecture whose folding/interpolation rate is 4 and 8, respectively. A cascaded preprocessing block is not only used in order to drive the high input signal frequency, but the resistive interpolation is also used to reduce the power consumption. Based on a novel self-calibrated vector generator, further, offset errors due to device mismatch, parasitic resistors. and parasitic capacitance can be reduced. The chip has been fabricated with a 1.2V 0.13um 1-poly 7-metal CMOS technology. The effective chip area including the calibration circuit is 2.5$mm^2$. SNDR is about 39.49dB when the input frequency is 9MHz at 2GHz sampling frequency. The SNDR is improved by 3dB with the calibration circuit.