• 전자공학회논문지A
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• 제32A권1호
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• pp.146-151
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• 1995

We have studied the fabrication self aligned atmospheric pressure(AP) CVD a-Si thin film transistor with source-drain ohmic contact by using ion shower doping method. The conductivity is 6*10$^{-2}$S/cm when the acceleration voltage, doping time and doping temperature are 6kV, 90s and 350.deg. C, respectively. We obtained the field effect mobility of 1.3cm$^{2}$/Vs and the threshold voltage of 7V.

• Journal of Ceramic Processing Research
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• 제19권5호
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• pp.361-368
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• 2018

We investigated the interfacial properties of fluorocarbon self-assembled monolayers (FC-SAMs) with different alkyl chain lengths. It was found that the substrate characteristics were changed rapidly with the fabrication time and temperature of the SAM. FC-3SAM, which has the shortest alkyl chain in this study, showed a contact angle of $54.1^{\circ}$ when it was fabricated in an electric oven at $60^{\circ}C$ for the first minute. The FC-3SAM showed a contact angle of up to $76.9^{\circ}$ when it was fabricated in an electric oven at the same temperature condition for 180 minutes. FC-10SAM, which has the longest alkyl chain in this study, showed a contact angle of $64.7^{\circ}$ when it was fabricated at a temperature condition of $60^{\circ}C$ for 1 minute, and a contact angle of $98.7^{\circ}C$ at a temperature condition of $60^{\circ}C$ for 180 minutes. It was found that the FC-10SAM shows an increased contact angle and hydrophobic properties due to a well-aligned molecular structure resulting from a strong van der Waals force. In contrast, the FC-3SAM shows a small contact angle due to the intermolecular disorder resulting from a weak van der Waals force. The average roughness of FC-SAMs was investigated using AFM. The surface roughness of FC-SAMs, which verifies the results of contact angle, was confirmed. At a fabrication time of 120 minutes, the FC-10SAM showed an improvement in average roughness by 62% compared to that of FC-3SAM due to its good alignment.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제38회 동계학술대회 초록집
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• pp.248-248
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• 2010

CMOS 축소화가 32nm node를 넘어서 지속적으로 진행되기 위하여 FinFET, Surround Gate and Tri-Gate와 같은 Fully Depleted 3-Dimensional 소자들이 SCE를 다루기 위해서 많이 제안되어 왔다. 하지만 소자의 축소화를 진행함에 있어서 좁고 균일한 patterning을 형성하는 것과 동시에 낮은 Extension Region과 Contact Region에서의 Series Resistance을 제공하여야 하고 Source/Drain Contact Formation을 확보하여야 한다. 그리고 소자의 축소화가 진행됨으로써 Silicide의 응집현상과 Source/Drain Junction의 누설전류에 대한 허용범위가 점점 엄격해지고 있다. ITRS 2005에 따르면 32nm CMOS에서는 Contact Resistivity가 대략 $2{\times}10-8{\Omega}cm2$이 요구되고 있다. 또한 Three Dimensional 소자에서는 Fin Corner Effect가 Channel Region뿐만 아니라 S/D Region에서도 중대한 영향을 미치게 된다. 따라서 본 논문에서 제시하는 Novel S/D Contact Formation 기술을 이용하여 Self-Aligned Dual/Single Metal Contact을 이루어Patterning에 대한 문제점 해결과 축소화에 따라 증가하는 Contact Resistivity 문제점을 해결책을 제시하고자 한다. 이를 검증하기3D MOSFET제작하고 본 기술을 적용하고 검증한다. 또한 Normal Doping 구조를 가진3D MOSFET뿐만 아니라 SCE를 해결하기 위해서 대안으로 제시되고 있는 SB-MOSFET을 3D 구조로 제작하고, 이 기술을 적용하여 검증한다. 그리고 Silvaco simulation tool을 이용하여 S/D에 Metal이 Contact을 이루는 구조가 Double type과 Triple type에 따라 Contact Resistivity에 미치는 영향을 미리 확인하였고 이를 실험으로 검증하여 소자의 축소화에 따라 대두되는 문제점들의 해결책을 제시하고자 한다.

• ETRI Journal
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• 제7권4호
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• pp.11-14
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• 1985

바이폴라 소자로 구성된 회로가 양호한 특성을 갖기 위해서는 개별 소자의 동작 속도, 집적도 및 전력 소비 특성이 좋아야 한다. 그런데 지금까지 주로 사용해온 기존의 SBC 바이폴라 트랜지스터로는 이들 특성을 개선하는 데는 한계가 있었다. 일반적으로 바이폴라 트랜지스터는 면적이 줄어듦에 따라 이들 특성이 개선되므로 본 연구에서는 SBC 방법과는 다른 PSA 공정 방법을 개발하였다. 즉, 소자 격리에서의 종래의 PN 접합에 의한 방법과 다른 산화막에 의한 방법을 도입하였고 또한 에미터, 베이스 사이의 거리를 최소로 줄이기 위하여 다결정 실리콘에 의한 polysilicon self-align 방법으로 에미터 및 베이스를 형성시켰다.

• 전자공학회논문지A
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• 제30A권6호
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• pp.38-48
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• 1993

A recessed n-p Juction diode with the self-aligned sturcture is proposed and fabricated by using the polysilicon as an n$^{+}$ diffusion source. The diode structure can be applicable to the emitter-base formation of high performance bipolar divice and the n$^{+}$ polysilicone mitter has an important effect on the device characteristics. The considered parameters for the polysilicon formation are the deposition condition. As$^{+}$ dose for the doping of the polysilicon and the annealing condition using RTP system. The vertical depth profiles of the fabricated diode are obtained by SIMS and the electrical characteristics are analyzed in terms of the ideality factor of diode (n), contact resistance and reverse leakage current. In addition, n$^{+}$-p junction diodes are formed by using the amorphous silicon (of combination of amorphous and polysiliocn) instead of polysilicon and their characteristics are compared with those of the standard sample. The As$^{+}$ dose for the formation of good junction is about 1~2${\times}10^{16}cm^{2}$ at given RTA conditions (1100.deg. C, 10sec).

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집
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• pp.358-361
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• 2002

Self-aligned MOSFETS using a polysilicon gate are widely fabricated in silicon technology. The polysilicon layer acts as a mask for the source and drain implants and does as gate electrode in the final product. However, the usage of polysilicon gate as a self-aligned mask is restricted in fabricating SiC MOSFETS since the following processes such as dopant activation, ohmic contacts are done at the very high temperature to attack the stability of the polysilicon layer. A metal instead of polysilicon can be used as a gate material and even can be used for ohmic contact to source region of SiC MOSFETS, which may reduce the number of the fabrication processes. Co-formation process of metal-source/drain ohmic contact and gate has been examined in the 4H-SiC based vertical power MOSFET At low bias region (<20V), increment of leakage current after RTA was detected. However, the amount of leakage current increment was less than a few tens of ph. The interface trap densities calculated from high-low frequency C-V curves do not show any difference between w/ RTA and w/o RTA. From the C-V characteristic curves, equivalent oxide thickness was calculated. The calculated thickness was 55 and 62nm for w/o RTA and w/ RTA, respectively. During the annealing, oxidation and silicidation of Ni can be occurred. Even though refractory nature of Ni, 950$^{\circ}C$ is high enough to oxidize it. Ni reacts with silicon and oxygen from SiO$_2$ 1ayer and form Ni-silicide and Ni-oxide, respectively. These extra layers result in the change of capacitance of whole oxide layer and the leakage current

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1994년도 춘계학술대회 논문집
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• pp.152-153
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• 1994

A recessed $n^{+}$-p junction diode with the serf-aligned structure is proposed and fabricated by using the polysilicon as an $n^{+}$ diffusion source. The diode structure can be applicable to the emitter-base formation of high performance bipolar device and the $n^{+}$ polysilicon emitter has an important effect on the device characteristics. The considered parameters for the polysilicon formation are the deposition condition $As^{+}$ dose for the doping of the polysilicon, and the annealing using RTP system. The vertical depth profiles of the fabricated diode are obtained by SIMS. The eleotrical characteristics are analyzed in trims of the ideality factor of diode (n), contact resistance arid reverse leakage current. The $As_{+}$ dose for the formation of good junction is current. The $As^{+}$ dose for the formation of goodjunctions is about 1∼2${\times}$$10^{16}$$cm^{-2}$ at given RTA condition ($1100^{\circ}C$, 10 sec). The $n^{+}$-p structure is successfully applied to the self-aligned bipolar device adopting a single polysilicon technology.

• 한국정보전자통신기술학회논문지
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• 제11권6호
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• pp.671-677
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• 2018

In this paper, we investigated the vertical alignment characteristics of liquid crystals (LCs) on fluorinated self-assembled monolayers (FSAMs). For comparison, a commercialized homeotropic polyimide (PI) layer was used as an LC alignment layer. We confirmed the successful deposition of FSAMs and the change of FSAMs before and after rubbing treatment through contact angle measurement and atomic force microscopy. The optical transmittance spectrum of the FSAMs is similar to that of the homeotropic PI layer, which is a superior optical characteristic applicable to LC devices. When FSAMs were applied to the vertically aligned (VA) LC cell, uniform and vertical LC alignments were achieved. In addition, the voltage-transmittance characteristic of VA LC cell with FSAMs was superior to that of VA LC cell with the conventional homeotropic PI layers. These results indicate that the FSAMs are suitable as the homeotropic LC alignment layer for enhanced LC devices.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권2호
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• pp.283-287
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• 2017

Recently, Ni-InGaAs has been required for high-performance III-V MOSFETs as a promising self-aligned material for doped source/drain region. As downscaling of device proceeds, reduction of contact resistance ($R_c$) between Ni-InGaAs and n-InGaAs has become a challenge for higher performance of MOSFETs. In this paper, we compared three types of sample, vacuum, 2% $H_2$ and 4% $H_2$ annealing condition in rapid thermal annealing (RTA) step, to verify the reduction of $R_c$ at Ni-InGaAs/n-InGaAs interface. Current-voltage (I-V) characteristic of metal-semiconductor contact indicated the lowest $R_c$ in 4% $H_2$ sample, that is, higher current for 4% $H_2$ sample than other samples. The result of this work could be useful for performance improvement of InGaAs n-MOSFETs.

• The Korean Journal of Ceramics
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• 제4권1호
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• pp.43-46
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• 1998

We have investigated the formation and thermal stability of cobalt aluminide(CoAl) thin films on GaAs. In order to obtain cobalt-aluminide thin films, we deposited a multilayer of Co/Al on GaAs, and subsequently annealed the samples at 80$0^{\circ}C$ for 30 min. After annealing, single-phase cobalt aluminide was produced showing a flat and uniform interface with GaAs. which indicates that cobalt aluminide (CoAl) is thermally stable with GaAs. In addition, the adherence and mechanical properties of the as-deposited, and annealed Co/Al multilayer structure on GaAs are compatible with those required for device fabrication processes. The electrical property of the CoAl/GaAs contact shows rectifying characteristics, indicating that the diodes were usable as rectifying gate electrodes.