• 한국정보디스플레이학회:학술대회논문집
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• 2000.01a
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• pp.65-66
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• 2000

Various fluoride films on a glass substrate were prepared and characterized to provide a seed layer for crystalline Si film growth. The XRD analysis on $CaF_2/glass$ illustrated (220) preferential orientation and showed lattice mismatch less than 5 % with Si. We achieved a fluoride film with breakdown electric field of 1.27 MV/cm, leakage current density about $10^{-6}$ $A/cm^2$, and relative dielectric constant less than 5.6. This paper demonstrates microcrystalline silicon $({\mu}c-Si)$ film growth by using a $CaF_2/glass$ substrate. The ${\mu}c-Si$ films exhibited crystallization in (111) and (220) planes, grain size of $700\;{\AA}$, crystalline volume fraction over 65 %, dark- and photo-conductivity ratio of 124, activation energy of 0.49 eV, and dark conductivity less than $4{\times}10^{-7}$ S/cm.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2013.05a
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• pp.68-69
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• 2013

금속 씨드 층(seed layer)을 직경 $10{\mu}m$, 깊이 $100{\mu}m$, 고종횡비 10:1 비아에 스퍼터링하였다. 금속 씨드 층의 두께는 스퍼터링 시간, 압력, 및 타겟파워를 변화하여 조절하였다. 금속 씨드층 스퍼터링 후 전기도금에 의해 구리 충전을 시도하였다. 비아의 고종횡비가 증가하면 비아 폭이 좁아져 비아의 하부층과 하단 측면 두께는 비아 상부 측면 두께만큼 충분하지 않아 문제가 될 수 있다. 스퍼터링 조건을 최적화 함으로써 씨드층의 특성을 높이고, 비아 홀 지름의 감소 속도를 줄일 수 있었다. 종래의 스퍼터링 방식을 이용하여 비아 입구의 opening percentage를 약 64%로 하고, 하부 씨드층 두께가 46.7 nm 인 금속 씨드층을 형성할 수 있었다. 이 씨드층 상에 전기도금으로 Cu filling을 성공적으로 할 수 있었다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.34 no.5
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• pp.333-336
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• 2021

Oxide YBCO bulk superconductors are manufactured using the melt process. Because seed crystal growth method utilizes a slow-spreading layer-by-layer reaction, a long-term heat treatment is required to manufacture a single-crystal specimen of several cm. In this study, the melt process method was applied to compensate for the shortcomings of the seed crystal growth method. The thickness of the upper and lower pellets of the YBCO bulk was molded to 40 mm, and YBCO superconductor was produced by heat treatment. The measurement results of capture magnetism was in line with the literature. This results in a relationship that the higher the growth of Y211 particle in the YBCO, the higher the superconducting properties. We analyzed the YBCO superconductor, focusing on the Y₂BaCuO₅ particle distribution.

• Proceedings of the Korean Magnestics Society Conference
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• 1998.05a
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• pp.26-27
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• 1998

• Proceedings of the Korean Magnestics Society Conference
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• 1999.10a
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• pp.138-139
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• 1999

• Proceedings of the KSME Conference
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• 2004.04a
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• pp.978-982
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• 2004

We present high aspect ratio 100nm-scale nickel stamper using e-beam lithography process and Cr/Qz mask for the injection molding process of nano grating patterns. Conventional photolithography blank mask (CrON/Cr/Qz) consists of quartz substrate, Cr layer of UV protection and CrON of anti-reflection layer. We have used Cr/Qz blank mask without anti-reflection layer of CrON which is non-conductive material and ebeam lithography process in order to simplify the nickel electroplating process. In nickel electroplating process, we have used Cr layer of UV protection as seed layer of nickel electroplating. Fabrication conditions of photolithography mask using e-beam lithography are optimized with respect to CrON/Cr/Qz blank mask. In this paper, we have optimized e-beam lithography process using Cr/Qz blank mask and fabricated nickel stamper using Cr seed layer. CrON/Cr/Qz blank mask and Cr/Qz blank mask require optimal e-beam dosage of $10.0{\mu}C/cm^2$ and $8.5{\mu}C/cm^2$, respectively. Finally, we have fabricated $116nm{\pm}6nm-width$ and $240nm{\pm}20nm-height$ nickel grating stamper for the injection molding pattern.

• Proceedings of the Materials Research Society of Korea Conference
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• 2010.05a
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• pp.58.1-58.1
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• 2010

We have developed a novel crystallization process, where the crystallization temperature is lowered compared to the conventional RTA process and the metal contamination is lowered compared to the conventional VIC process. A very-thin a-Si film was deposited and crystallized at $550^{\circ}C$ for 3 h by the VIC process and then a thick a-Si film was deposited and crystallized by the RTA process at $680^{\circ}C$ for 5 min using the VIC poly-Si layer as a crystallization seed layer. The RTA crystallized temperature could be lowered up to $50^{\circ}C$, compared to RTA process alone. The poly-Si film appeared a needle-like growth front and relatively well-arranged (111) orientation. In addition, the Ni concentration in the poly-Si film was lowered to $3{\times}10^{17}\;cm^{-3}$ and that at the poly-Si/$SiO_2$ interface was lowered to $5{\times}10^{19}\;cm^{-3}$. The reduction in metal contamination could be greatly helpful to achieve a low leakage current in poly-Si TFT, which is the critical parameter for commercialization of AMOLED.

• Proceedings of the KIEE Conference
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• 1993.11a
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• pp.204-206
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• 1993

In this paper we represented electroplating process without seed layers for making metal micro structures needed for applying terminal voltage for one-to-one cell fusion system. In this system, we need thick insulator and metal structures because the diameter of a cell is approximately $40{\mu}m$. So, we adopted the photo-sensitive polyimide as electroplating molds and structural material. Generally, the processes utilizing the photo-sensitive polyimide as molds have metal seed layers on the substrate as electroplating electrodes and requires wiring tasks to these seed layers. We proposed electroplating process without any seed layer on the Si-substrate and simulated P-N-P (electrode - Si substrate - electrode) junction on N-type silicon substrate. Leakage current from one metal structure to another which arise when terminal voltage is applied can be remarkably decreased by doping Boron in the region to be electroplated.

• Proceedings of the Korean Vacuum Society Conference
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• 1999.07a
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• pp.103-103
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• 1999

CeO2 는 cubic 구조의 일종인 CeF2 구조를 가지며 격자 상수가 0.541nm로 Si의 격자 상수 0.543nm와 거의 비슷하여 Si과의 부정합도가 0.35%에 불과하여 CeO2를 Si 기판 위에 에피택셜하게 성장시킬 수 있는 가능성이 크다. 따라서 SOI(Silicon-On-Insulator) 구조의 실현을 위하여 Si 기판위에 CeO2를 에피택셜하게 성장시키려는 많은 노력이 있었다. 또한 CeO2 는 열 적으로 대단히 안정된 물질로서 금속/강유전체/반도체 전계효과 트랜지스터(MFSFET : metal-ferroelectric-semiconductor field effect transistor)에서 ferroelectric 박막과 Si 기판사이에 완충층으로 사용되어 강유전체의 구성 원자와 Si 원자들간의 상호 확산을 방지함으로써 경계면의 특성을 향상시기키 위해 사용된다. e-beam evaporation와 laser ablation에 의한 Si 기판 위의 CeO2 격자 성장에 관한 많은 보고서가 있다. 이 방법들은 대규모 생산 공정에서 사용하기 어려운 반면 RF-magnetron sputtering은 대규모 반도체 공정에 널리 쓰인다. Sputtering에 의한 Si 기판위의 CeO2 막의 성장에 관한 보고서의 수는 매우 적다. 이 논문에서는 Ce target을 사용한 reactive rf-magnetron sputtering에 의해 Si(100) 과 Si(111) 기판위에 성장된 CeO2 의 구조 및 전기적 특성을 보고하고자 한다. 주요한 증착 변수인 증착 power와 증착온도, Seed Layer Time이 성장막의 결정성에 미치는 영향을 XRD(X-Ray Diffractometry) 분석과 TED(Transmission Electron Diffration) 분석에 의해 연구하였고 CeO2 /Si 구조의 C-V(capacitance-voltage)특성을 분석함으로써 증차된 CeO2 막과 실리콘 기판과의 계면 특성을 연구하였다. CeO2 와 Si 사이의 계면을 TEM 측정에 의해 분석하였고, Ce와 O의 화학적 조성비를 RBS에 의해 측정하였다. Si(100) 기판위에 증착된 CeO2 는 $600^{\circ}C$ 낮은 증착률에서 seed layer를 하지 않은 조건에서 CeO2 (200) 방향으로 우선 성장하였으며, Si(111) 기판 위의 CeO2 박막은 40$0^{\circ}C$ 높은 증착률에서 seed layer를 2분이상 한 조건에서 CeO2 (111) 방향으로 우선 성장하였다. TEM 분석에서 CeO2 와 Si 기판사이에서 계면에서 얇은 SiO2층이 형성되었으며, TED 분석은 Si(100) 과 Si(111) 위에 증착한 CeO2 박막이 각각 우선 방향성을 가진 다결정임을 보여주었다. C-V 곡선에서 나타난 Hysteresis는 CeO2 박막과 Si 사이의 결함때문이라고 사료된다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.7
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• pp.793-796
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• 2004

In order to improve c-axis crystalline orientation and high perpendicular coercivity of deposited ${Co}_77{Cr}_20{Ta}_3$perpendicualr recording layer, Two step method was investigated using a Facing Targets Sputtering System(FTS). The ${\Delta\theta}_50$ of ${Co}_77{Cr}_20{Ta}_3$recording layer deposited on seedlayer prepared at Room Temperature was as low as $5^\circ$, while that of the recording layer without seedlayer was about 11$^{\circ}$. The Two-Step method using ${Co}_77{Cr}_20{Ta}_3$seedlayer prepared at Room Temperature was shown to be very effective in controling the c-axis orientation of ${Co}_77{Cr}_20{Ta}_3$ recording layer with thin thickness.