• Progress in Superconductivity
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• v.1 no.2
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• pp.105-109
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• 2000

We have designed and fabricated a single-flux-quantum(SFQ) four-stage shift register using YBCO bicrystal Josephson junctions, and tested its operations using a digital measurement set-up. The circuit consists of 4 shift register stages and a read SQUID placed next to each side of the shift register. Each SQUID was inductively coupled to the nearby shift register stage. The major obstacle in testing the circuits was the interference between the two read SQUIDs, and we could get over the problem by determining the correct operation points of the SQUID from the simultaneously measured modulation curves. Loaded data ('1' or '0') were successfully shifted from a stage to the next by a controlled current pulse injected to the bias lines located between the stages, and the corresponding correct data shifts were observed with the two read SQUIDs.

• Journal of Korean Library and Information Science Society
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• v.20
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• pp.241-284
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• 1993

Through the restoration, we can find that the register of houses, inhabitants and their ancestry, which is in the Sunsung Kim family registers, was fundamentally the census register of Kim Roe including more ancestry transformed into the lists of house, inhabitants and their ancestry of Kim Roe, Kim Bang-Seek, Kim Sung-Sae and Kim Hee-Bo. And we can find also the original forms were considerably damaged. That is, in the course of transformation, considerable parts of the contents of ancestry were not needed, so they were removed, the recordings of brotherandsisters, sons and their servants were also removed. By comparing of the restored census register of Kim Roe and the Sunsung Kim family registers, we can know the fact that when they published the family registers, the contents of the founder to the ninth descendants were totally depended on the census register of Kim Roe. The Census Register of King Taejo of Choson Dynasty(National Treasure No. 131) which has been recorded almost same periods as the census register of Kim Roe was remained as an original state. Therefore, it was greatly helpful for restoring the census register of Kim Roe. There were few materials which we can know the way of ordinary life in Koryo period. But through the census register of Kim Roe and the census Register of King Taejo of Choson Dynasty, we have a glimpse of their life history. Nevertheless we can find some demerits in the census register of Kim Roe as followers : First, it is not an original but a transformed one, while the Census Register of King Taejo of Choson Dynasty is first materials. Second, it was recorded the only one family. Finally, it was omitted the parts of his brotherandsisters, children and servants who lived with their master. According to these demerits its worth of materials for history will be descended more or less. Therefore, when we use this material, we should treat it more considerably.

• Journal of Computing Science and Engineering
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• v.5 no.2
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• pp.121-130
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• 2011

Recent research indicates that transient errors will increasingly become a critical concern in microprocessor design. As embedded processors are widely used in reliability-critical or noisy environments, it is necessary to develop cost-effective fault-tolerant techniques to protect processors against transient errors. The register file is one of the critical components that can significantly affect microprocessor system reliability, since registers are typically accessed very frequently, and transient errors in registers can be easily propagated to functional units or the memory system, leading to silent data error (SDC) or system crash. This paper focuses on investigating the impact of register file soft errors on system reliability and developing cost-effective techniques to improve the register file immunity to soft errors. This paper proposes the register vulnerability factor (RVF) concept to characterize the probability that register transient errors can escape the register file and thus potentially affect system reliability. We propose an approach to compute the RVF based on register access patterns. In this paper, we also propose two compiler-directed techniques and a hybrid approach to improve register file reliability cost-effectively by lowering the RVF value. Our experiments indicate that on average, RVF can be reduced to 9.1% and 9.5% by the hyperblock-based instruction re-scheduling and the reliability-oriented register assignment respectively, which can potentially lower the reliability cost significantly, without sacrificing the register value integrity.

• Progress in Superconductivity
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• v.3 no.1
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• pp.83-86
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• 2001

We have fabricated a single flux quantum 4-stage shift register with interface-controlled $Y_1$$Ba_2$$Cu_3$$O_{7-x}$(YBCO) Josephson junction. The YBCO Josephson junctions showed RSJ-like current-voltage(I-V) curves at temperatures 45~80K. We tested load and shift operation of shift register with binary data sequences “1000”, “1010”, “1011”, and “1111” at 58K. For all the binary data sequences, the shift register operated successfully. By operating the circuit with proper current pulses, we observed no errors during at least 12 hours operation for all the data sequences.s.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.8
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• pp.121-127
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• 2013

Memory devices including SRAM and DRAM are very susceptible to high energy radiation particles in the space. Abnormal operation of the devices is caused by SEE or TID. This paper presents a method to estimate proton SEU cross section representing the susceptibility of the latch circuit that the unit cell of the SRAM and proposes a new latch circuit to mitigate the SEU. 50b shift register was fabricated by using the conventional latch and the proposed latch in $0.35{\mu}m$ process. Irradiation experiment was conducted at KIRAMS by using 43MeV proton beam. It was found that the proposed latch-shift register is not affected by the radiation environment compared to the conventional latch-shift register.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.302-305
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• 2000

This paper proposed an optimal register resource allocation algorithm using graph coloring for minimal register at high level synthesis. The proposed algorithm constructed interference graph consist of the intermediated representation CFG to description VHDL. and at interference graph fur the minimal select color selected a position node at stack, the next inserted spill code and the graph coloring process executes for optimal register allocation. The proposed algorithm proves to effect that result compare another allocation techniques through experiments of bench mark.

• 한국초전도학회:학술대회논문집
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• v.9
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• pp.102-106
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• 1999

We have designed and fabricated a four-bit shift register circuit using YBCO bicrystal junctions and experimentally tested its operations by a computer-controlled digital measurement set-up. Laser ablated YBCO thin films with clean surface were used in this work. The circuit consists of the shift register and two read SQUIDs placed next to each sides of the shift register. The SQUIDs were inductively coupled to the nearby shift register stages. A probe equipped with high speed coax lines were used in this experiment. The major obstacle in testing the circuit was the interference between the read SQUIDs and we solved the problem by finding the correct operation points of the SQUIDs from the simultaneously measured modulation curves. Loaded Data("1" or "0") were successfully shifted from a stage to the next one by a controlled current pulse injected to the bias lines located between the stages and the data shifts were correctly monitored by the read SQUIDs

• The KIPS Transactions:PartA
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• v.8A no.2
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• pp.107-116
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• 2001

A multithreaded model is a hybrid one which combines locality of execution of the von Neumann model with asynchronous data availability and implicit parallelism of the dataflow model. Much researches that have been made toward the advanced performance of multithreaded models are about the cache memory which have been proved to be efficient in the von Neumann model. To use an instruction cache or operand cache, the multithreaded models must have cache memories. If cache memories are added to the multithreaded model, they may have the disadvantage of high implementation cost in the mode. To solve these problems, we did not add cache memory but applied the method of executing the caching by using available registers of the multithreaded models. The available register-based caching method is one that use the registers which are not used on the execution of threads. It may accomplish the same effect as the cache memory. The multithreaded models can compute the number of available registers to be used during the process of the register optimization, and therefore this method can be easily applied on the models. By applying this method, we can also remove the access conflict and the bottleneck of frame memories. When we applied the proposed available register-based caching method, we found that there was an improved performance of the multithreaded model. Also, when the available-register-based caching method is compared with the cache based caching method, we found that there was the almost same execution overhead.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.3
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• pp.148-152
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• 2009

Recent CMOS technology scaling has seriously eroded the bit-line noise immunity of register files due to the consequent increase in active bit-line leakage currents. To restore its noise immunity while maintaining performance, we propose and evaluate a $256{\times}40$-bit register file incorporating dual-$V_t$ bit-lines with a boosted gate overdrive voltage in 65 nm bulk CMOS technology. Simulation results show that the proposed bootsrapping scheme lowers leakage current by a factor of 450 without its performance penalty.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.4
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• pp.229-234
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• 2007

In this paper, we present an efficient instruction set architecture using vector register file hardware to accelerate operation of general matrix-vector operations in DSP microprocessor. The technique enables in-situ row-access as well as column access to the register files. It can reduce the number of memory access significantly. The technique is especially useful for block-based video signal processing kernels such as FFT/IFFT, DCT/IDCT, and two-dimensional filtering. We have applied the new instruction set architecture to in-loop deblocking filter processing in H.264 decoder. Performance comparisons show that the required load/store operations for the in-loop deblocking filter can be reduced about 42%. The architecture would improve the processing speed, and code density in DSP microprocessor especially for video signal processing substantially.