• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 신호처리소사이어티 추계학술대회 논문집
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• pp.433-436
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• 2003

In this paper, the efficient motion estimation and compensation method for 3 dimensional wavelet transform is proposed. Recently, since the compression performance and scalable functionality are provided by wavelet transform, many researches have been carried out for applying to the video compression. For the temporal filtering, motion estimation and compensation techniques are used, but the unconnected pixels, which are produced by motion compensation result into the degradation of coding performance and quality of the picture. For the efficient motion compensated temporal filtering by reducing the number of these unconnected pixels, we propose the variable block size motion estimation and compensation method. Also we propose a method that determines the block size using rate-distortion optimization technique according to the local characteristics of the frame. The simulation results show the improved performances than the MPEG-4 scalable coding methods and the 3 dimensional wavelet coding methods using fixed block size motion estimation and compensation.

• ETRI Journal
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• 제31권1호
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• pp.65-67
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• 2009

We introduce an advanced terrestrial digital multimedia broadcasting (AT-DMB) system that overcomes the limitation of data transmission rates of T-DMB by doubling it with the same frequency bandwidth. In this letter, we propose an efficient algorithm which generates a scalable transport stream in AT-DMB by multiplexing certain types of elementary streams encoded using scalable video coding and an MPEG-surround audio coder for high-quality multimedia services.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권2호
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• pp.177-183
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• 2015

A high speed VLSI digital Winner-Take-All (WTA) circuit called simultaneous digital WTA (SDWTA) circuit is presented in this paper. A minimized comparison-cell (w-cell) is developed to reduce the size and to achieve high-speed. The w-cell which is suitable for VLSI implementation consists of only four transistors. With a minimized comparison-cell structure SDWTA can compare thousands of data simultaneously. SDWTA is scalable with O(mlog n) time-complexity for n of m-bit data. According to simulations, it takes 16.5 ns with $1.2V-0.13{\mu}m$ process technology in finding a winner among 1024 of 16-bit data.

• 한국방송∙미디어공학회:학술대회논문집
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• 한국방송공학회 2009년도 IWAIT
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• pp.23-27
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• 2009

A scalable video coding (SVC) extension to the H.264/AVC standard has been developed by the Joint Video Team (JVT). SVC provides spatial, temporal and quality scalability with high coding efficiency and low complexity. SVC is now developing the extension of the first version including color format scalability. The paper proposes to remove some luminance related header and luminance coefficients when an enhancement layer adds only additional color information to its lower layer. Experimental results shows 0.6 dB PSNR gain on average in coding efficiency compared with an approach using the existing SVC standard.

• 한국방송∙미디어공학회:학술대회논문집
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• 한국방송공학회 2009년도 IWAIT
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• pp.413-417
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• 2009

The use of scalable video coding scheme has been regarded as a promising solution for guaranteeing the quality of service of the video streaming over the Internet because it is a capable coding scheme to perform quality adaptation depending on network conditions. In this paper, we use a streaming model that transmits base layer using TCP and enhancement layers using DCCP, which try to provide transmission reliability of the BL and TCP friendliness. Unlike pervious works, the proposed algorithm performs rate adaptation based on playout buffer status. The PoB status of the client is sent back periodically to the server and serves as a network congestion indicator. Experimental results show that our scheme improves streaming quality comparing with pervious scheme in the case of not only constant/dynamic background flows but also VBR-encoded video sequence.

• 한국방송∙미디어공학회:학술대회논문집
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• 한국방송공학회 1997년도 Proceedings International Workshop on New Video Media Technology
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• pp.43-48
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• 1997

The video transmission for real-time viewing over the Internet is a core operation for the multimedia services. However, its realization is very difficult because the Internet has two major problems, namely, very narrow endpoint-bandwidth and the network jitter. We already proposed a scalable video transmission method in [8] which used MPEG-4 video VM(Verification Model) 2.0[3] for very low bit rate coding and an adaptive temporal rate control of video objects to overcome the network jitter problem. In this paper, we present the improved adaptive temporal rate control scheme for the scalable transmission. Experimental results for three test video sequences show that the adaptive temporal rate control can transfer the video bitstream at source frame rate under variable network condition.

• Journal of Electrical Engineering and information Science
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• 제2권4호
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• pp.8-13
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• 1997

This paper describes a scalable systolic synchronous memory for digital signal processing and packet switching. The systolic synchronous memory consists of the 2-D array of small memory blocks which are fully pipelined and communicated in three directions with adjacent blocks. The maximum delay of a small memory block becomes the operation speed of the chip. The array configuration is scalable for the entire memory size requested by an application. it has the initial latency of N+3 cycles with NxN array configuration. We designed an experimental 200 MHz 4Kb static RAM chip with the 4x4 array configuration of 256 SRAM blocks. It was fabricated is 0.8$\mu\textrm{m}$ twin-well single-poly double-metal CMOS technology.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2018년도 전력전자학술대회
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• pp.30-32
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• 2018

본 논문은 Modular Scalable Inverter System(MSIS)에서 두 인버터 간에 캐리어 위상차로 인해 순환전류가 발생할 시 고주파 전압 보상을 이용한 순환전류 저감기법을 제안한다. MSIS는 인버터를 병렬로 구성하여 전력용량을 증가시키고 필요에 따라 선택적으로 사용하여 효율을 높인다. 하지만 병렬 인버터 구조에서는 필연적으로 순환전류가 발생하여 고주파 전압 보상을 이용하여 두 인버터가 동일한 스위칭 패턴을 출력하게 하여 주파수 성분의 순환전류를 저감한다. 제안한 방법의 유효성은 600W IPMSM를 부하로 한 MSIS 축소 모델에서 시뮬레이션을 통해 검증하였다.

• ETRI Journal
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• 제18권3호
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• pp.107-125
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• 1996

In this paper, we define the general requirements of ATM switching systems such as scalability, distributed fashion, and modularity. Also we propose a practical implementation of a scalable ATM switching system whose capacity can be easily expanded. Firstly, the architecture of the system is discussed with an emphasis on system scalability, modularity of subsystems and the simple control network of the design requirements. Secondly, we suggest the three types of distributed call/connection control schemes that are suitable for our switching system. We also estimate their call processing capacity on the average and make a comparison of them under the various system architectures. Since our scalable switching system can be constructed to perform the call processing functions on the various levels of the system capacity, it has much adaptability at the various evolution phases or regions of the network environment.

• ETRI Journal
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• 제28권2호
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• pp.145-154
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• 2006

In the decoding process associated with interframe wavelet coding, the inverse wavelet transform requires high computational complexity. However, as video technology starts to pervade all aspects of our lives, decoders are becoming required in various devices such as PDAs, notebooks, PCs, and set-top boxes. Therefore, a decoder's complexity needs to be adapted to the processor's computational power, and consequently a low-complexity codec is also required for scalable video coding. In this paper, we propose a method of controlling and lowering the complexity of the spatial wavelet transform while sustaining the same coding efficiency as that currently afforded. In addition, the proposed method may alleviate the ringing effect for slowly changing image sequences.