• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.7
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• pp.1448-1452
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• 2004

In this paper, a photodiode capable of obtaining a sufficient photo/ dark current ratio at both a forward bias state and a reverse bias state is proposed. The photodiode includes a glass substrate, an Cr thin film formed as a lower electrode over the glass substrate, Cr silicide thin film(∼l00$\AA$) ) formed as a schottky barrier over the Cr thin film, a hydrogenated amorphous silicon film formed as a photo conduction layer over a portion of the Cr silicide thin film. Transparent conduction film ITO (thickness 100nm) formed as an upper electrode over the hydro-generated amorphous silicon film is then deposited in pure argon at room temperature for the Schottky contact and light window. The high quality Cr silicide thin film using annealing of Cr and a-Si:H is formed and analyzed by experiment. We have obtained the film with a superior characteristics. The dark current of the ITO/a-Si:H Schottky at a reverse bias of -5V is ∼3$\times$IO-12 A/un2, and one of the lowest reported, hitherto. AES(Auger Electron Spectroscophy) measurements indicate that this notable improvement in device characteristics stems from reduced diffusion of oxygen, rather than indium, from the ITO into the a-Si:H layer, thus, preserving the integrity of the Schottky interface. The spectral response of the photodiode for wavelengths in the range from 400nm to 800nm shows the expected behavior whereby the photocurrent is governed by the absorption characteristics of a-Si:H.

• Journal of the Korean Vacuum Society
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• v.12 no.4
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• pp.239-250
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• 2003

The reliability degradation phenomena in the SiGe hetero-junction bipolar transistor (HBT) are investigated in this review. In the case of the SiGe HBT the decrease of the current gain, the degradation of the AC characteristics, and the offset voltage are frequently observed, which are attributed to the emitter-base reverse bias voltage stress, the transient enhanced diffusion, and the deterioration of the base-collector junction due to the fluctuation in fabrication process, respectively. The reverse-bias stress on the emitter-base junction causes the recombination current to rise, increasing the base current and degrading the current gain, because hot carriers formed by the high electric field at the junction periphery generate charged traps at the silicon-oxide interface and within the oxide region. Because of the enhanced diffusion of the dopants in the intrinsic base induced by the extrinsic base implantation, the shorter distance between the emitter-base junction and the extrinsic base than a critical measure leads to the reduction of the cut-off frequency ($f_t$) of the device. If the energy of the extrinsic base implantation is insufficient, the turn-on voltage of the collector-base junction becomes low, in the result, the offset voltage appears on the current-voltage curve.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.5
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• pp.519-525
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• 2015

Positive bias stress-induced instability in amorphous indium-gallium-zinc-oxide (a-IGZO) bottom-gate thin-film transistors (TFTs) was investigated under high $V_{GS}$/low $V_{DS}$ and low $V_{GS}$/high $V_{DS}$ stress conditions through incorporating a forward/reverse $V_{GS}$ sweep and a low/high $V_{DS}$ read-out conditions. Our results showed that the electron trapping into the gate insulator dominantly occurs when high $V_{GS}$/low $V_{DS}$ stress is applied. On the other hand, when low $V_{GS}$/high $V_{DS}$ stress is applied, it was found that holes are uniformly trapped into the etch stopper and electrons are locally trapped into the gate insulator simultaneously. During a recovery after the high $V_{GS}$/low $V_{DS}$ stress, the trapped electrons were detrapped from the gate insulator. In the case of recovery after the low $V_{GS}$/high $V_{DS}$ stress, it was observed that the electrons in the gate insulator diffuse to a direction toward the source electrode and the holes were detrapped to out of the etch stopper. Also, we found that the potential profile in the a-IGZO bottom-gate TFT becomes complicatedly modulated during the positive $V_{GS}/V_{DS}$ stress and the recovery causing various threshold voltages and subthreshold swings under various read-out conditions, and this modulation needs to be fully considered in the design of oxide TFT-based active matrix organic light emitting diode display backplane.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.1-5
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• 2010

In this paper, we directly compare the program efficiency of conventional channel hot electron (CHE) injection methods and a novel hot electron injection methods using substrate forward biases in our silicon-oxide-nitride-oxide-silicon (SONOS) cell. Compared with conventional CHE injection methods, the proposed injection method showed improved program efficiency including faster program operation at lower bias voltages as well as localized trapping features for multi-bit operation with a threshold voltage difference of 1 V at between the forward and reverse read. This program method is expected to be useful and widely applied for future nano-scale multi-bit SONOS memories.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.26 no.2
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• pp.523-531
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• 2016

This paper studies the empirical relationship between various privacy protection measures and personal information invasion experience of firms and individuals using rich and heterogeneous survey data. By analyzing PSM models. we get the following results: first, the treatment group which have more technical measures and/or IS investment tends to experience more privacy invasion than the control group which have less of them. second, the reverse causality, that is firms and individuals with more experience of privacy invasion tends to take more measure for personal information protection, is found to exist. From these result, we discuss proper privacy policies implications in respects of attackers benefits and individual irrationality.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.1
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• pp.13-20
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• 2000

In this paper, we demonstrated an analytical description method of forward votage drop and reverse leakage current of the junction barrier controlled schottky rectifier with linearly graded junction and abrupt junction models. In this case, the vertical depths of device are 1[${\mu}{\textrm}{m}$] and 2[${\mu}{\textrm}{m}$], respectively. Through ion implantation and annealing process, we obtain the data of lateral and depth from implanted 2-dimensional profiles. Also we applied these data to models that indicate the change of depletion each on linearly-graded and abrupt juction as the forward and revers bias. After applied depletion changes to electric characteristics of JBS rectifiers, we calculated the forward I-V, the reverse leakage current and temperatures vs. power dissipations according to each junction. When we compared the rectifier with calculated and measured data, from the calculated results, forward votage drop with linearly graded junction is lower than that of abrupt junction and reverse leakage current with linearly graded junction is lower(≒1$\times$10\ulcorner times) than that of abrupt junction. Also, the power dissipations according to different juction depth(1[${\mu}{\textrm}{m}$], 2[${\mu}{\textrm}{m}$]) of device are calculated. Seeing the calculated results, we confirmed it from analytic model that the rectifier with linearly graded junction retained a low power dissipation up to 600[$^{\circ}C$] in comparison with the rectifier with abrupt junction.

• Journal of information and communication convergence engineering
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• v.5 no.2
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• pp.116-120
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• 2007

In this paper, the image sensor using the a-Si:H TFT is proposed. The optimum amorphous silicon thin film is deposited using plasma enhanced chemical vapor deposition (PECVD). TFT and photodiode both with the thin film are fabricated and form image sensor. The photodiode shows that $I_{dark}\;is\;{\sim}10^{-13}\;A,\;I_{photo}\;is\;{\sim}10^{-9}\;A\;and\;I_{photo}/I_{dark}\;is\;{\sim}10^4$, respectively. In the case of a-Si:H TFT, it indicates that $I_{on}/I_{off}\;is\;10^6$, the drain current is a few ${\mu}A\;and\;V_{th}\;is\;2{\sim}4$ volts. For the analysis on the fabricated image sensor, the reverse bias of -5 volts in ITO of photodiode and $70 {\mu}sec$ pulse in the gate of TFT are applied. The image sensor with good property was conformed through the measured photo/dark current.

• Proceedings of the KIEE Conference
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• 1999.07d
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• pp.1910-1912
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• 1999

This paper was described electrical characteristics of Metal/GaN contact for application of GaN thin films. The lowest contact resistivity was $1.7\times10^{-7}[\Omega-cm^2]$ at Ti/Al Structure. Mean while, GaN MESFETs have been fabricated with a 250 nm thick channel on a high resistivity GaN layer grown by GAIVBE system. For a gate-source diode reverse bias of 35 V, the gate leakage current was $120{\mu}A$. From the data, we estimate the transconductance for our GaN MESFET to be 25 mS/mm.

• Proceedings of the IEEK Conference
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• 2004.08c
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• pp.460-462
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• 2004

The control of the data retention time is a main issue for realizing future high density dynamic random access memory. There are several leakage current mechanisms in which the stored data disappears. The mechanisms of data disappear is as follow, 1 )Junction leakage current between the junction, 2) Junction leakage current from the capacitor node contact, 3)Sub-threshold leakage current if the transfer transistor is affected by gate etch damage etc. In this paper we showed the plasma edge damage effect to find out data retention time effectiveness. First we measured the transistor characteristics of forward and reverse bias. And junction leakage characteristics are measured with/without plasma damage by HP4145. Finally, we showed the comparison TRET with etch damage, damage_cure_RTP and hydrogen_treatment. As a result, hydrogen_treatment is superior than any other method in a curing plasma etch damage side.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.8
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• pp.15-25
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• 1997

The integration method of carier concentrations to redcue the discretization error of th box integratio method used in the discretization of the three-dimensional poisson's equation is presented. The carrier concentration is approximated in the closed form as an exponential function of the linearly varying potential in the element. The presented method is implemented in the three-dimensional poisson's equation solver running under the windows 95. The accuracy and the convergence chaacteristics of the three-dimensional poisson's equation solver are compared with those of DAVINCI for the PN junction diode and the n-MOSFET under the thermal equilibrium and the DC reverse bias. The potential distributions of the simulatied devices from the three-dimensional poisson's equation solver, compared with those of DAVINCI, has a relative error within 2.8%. The average number of iterations needed to obtain the solution of the PN junction diode and the n-MOSFET using the presented method are 11.47 and 11.16 while the those of DAVINCI are 21.73 and 23.0 respectively.