• Proceedings of the Korea Information Processing Society Conference
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• 2003.11b
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• pp.1033-1036
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• 2003

최근 인터넷의 급격한 발전의 결과로서 전산 시스템의 대규모화와 복잡화가 증가함에 따라 시스템의 전문적인 관리를 위한 솔루션에 대한 요구가 증가하고 있다. 서비스를 수행중인 시스템에 있어서 성능 관리는 전산 자원의 가동 성능을 유지하고 향상시키는 일련을 작업을 의미하며 모니터링, 진단, 제어의 사이클로 관리자와 상호작용을 수행한다. 본 논문에서는 차세대 인터넷 서버의 관리를 위한 시스템 관리 솔루션인 MATRlx (MATRIx's Advanced Technology of Resource Information extraction / eXploitation / eXploration / eXchange) 시스템을 소개하며 MATRIx 시스템의 성능 관리 블록인 MATRIx-PFMB의 설계 및 구현에 대한 이슈들을 다룬다. MATRIx-PFMB(PerFormance Management Block)는 관리 서버와 에어젼트 및 관리자 콘솔로 구성되며 능동적인 시스템 관리를 위한 진단 도구 및 제어 기능을 제공하고 기능 확장의 용이성을 제공하기 위한 프레임워크 구조를 갖는다.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.339-342
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• 2000

This paper presented a FPGA design of SEED, which is the Korea standard 128-bit block cipher. In this work, SEED was designed technology- independently for other applications such as ASIC or core-based designs. Hence in case of changing the target of design, it is not necessary to modify design or need only minor modification to reuse the design. Since SEED algorithm requires a lot of hardware resources, each unit was designed only once and used sequentially. So, the number of gates was minimized and SEED algorithm was fitted in FPGA without additional components. It was confirmed that the rate of resource usage is about 80% in ALTERA 10KE and the SEED design operates in a clock frequency of 131.57 MHz and an encryption rate of 29 Mbps.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.5
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• pp.681-691
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• 1986

To represent the relations of the data dependency and resource conflict among micro-operations(MOP's) in the compaction process of microprograms, we propose a DDM (data dependent matrix) representation method instead of the DAG (conventional directed acyclic graph). Also, we propose a global compaction algorithm of microprograms to prevent a kind of block copying by cutting the trace at a junction block. The DDM method and compaction algoristhm have been applied to the Lah's example. The results shows that the proposed algorithm is more efficient than the conventional algorithms in reducing in reducing the total execution time and control memory space.

• Journal of Ship and Ocean Technology
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• v.10 no.2
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• pp.37-44
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• 2006

The erection in shipbuilding is the process to assemble all the blocks one by one in certain order and requires more leveled and efficient schedule than other processes do. However, erection schedule includes too many constraints to be systemized with simple programs and constraints are changed frequently. These difficulties make it rare to find automatic erection schedule generation system with load leveling ability. In this paper, a CSP (Constraint Satisfaction Problem)-based load leveling algorithm using a maximum load diminution technique is proposed and applied to the block erection scheduling of a dock in a shipyard. The result shows that it performs better than currently used scheduling method based on empirical logics. The maximum load of welding length and crane usage are reduced by 31.63% and 30.00% respectively. The deviation of resource usage amount also decreases by 8.93% and 7.51%.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.26 no.3
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• pp.623-630
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• 2016

Heterogeneous IoT devices must satisfy a certain level of security for mutual connections and communications. However, a performance degradation of cryptographic algorithms in resource constrained devices is inevitable and so an optimization or efficient implementation method is necessary. In this paper, we study an efficient implementation method for rotation operations regarding registers for running ARX lightweight block ciphers. In a practical sense, we investigate the performance of modified rotation operations through experiments using real experiment devices. We show the improved performance of modified rotation operations and discover the significant difference in measured performance between simulations and real experiments, particularly for 16-bit MSP microcontrollers.

• KIPS Transactions on Computer and Communication Systems
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• v.9 no.5
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• pp.107-112
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• 2020

Ultra-lightweight password CHAM is an algorithm with efficient addition, rotation and XOR operations on resource constrained devices. CHAM shows high computational performance, especially on IoT platforms. However, lightweight block encryption algorithms used on the Internet of Things may be vulnerable to side channel analysis. In this paper, we demonstrate the vulnerability to side channel attack by attempting a first power analysis attack against CHAM. In addition, a safe algorithm was proposed and implemented by applying a masking technique to safely defend the attack. This implementation implements an efficient and secure CHAM block cipher using the instruction set of an 8-bit AVR processor.

• IE interfaces
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• v.24 no.1
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• pp.78-86
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• 2011

To mitigate space restriction and to raise productivity, some shipbuilding companies use floating-docks on the sea instead of dry-docks on the land. In that case, a floating-crane that can lift very heavy objects (up to 3,600 tons) is used to handle the blocks which are the basic units in shipbuilding processes, and so, very large blocks (these are called the mega-blocks) can be used to build a ship. But, because these mega-blocks can be made only in the area near the floating-dock and beside the sea, the space is very important resource for the process. Therefore, our problem is to make an efficient spatial schedule for the mega-block assembly yard. First of all, we formulate this situation into a mathematical model and find optimal solution for a small problem using a commercial optimization software. But, the software could not give optimal solutions for practical sized problems in a reasonable time, and so we propose a GA-based heuristic algorithm. Through a numerical experiment, finally, we show that the spatial scheduling algorithm can provide a very good performance.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.22 no.3
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• pp.485-494
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• 2012

The block cipher HIGHT is designed suitable for low-resource hardware implementation. It established as the TTA standard and ISO/IEC 18033-3 standard. In this paper, we propose a differentail fault attack against the block cipher HIGHT. In the proposed attack, we assume that an attacker is possible to inject a random byte fault in the input value of the 28-th round. This attack can recover the secret key by using the differential property between the original ciphertext and fault cipher text pairs. Using 7 and 12 error, our attack recover secret key within a few second with success probability 87% and 51%, respectively.

• Journal of The Geomorphological Association of Korea
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• v.26 no.2
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• pp.1-14
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• 2019

This study analyzed the relativity between block stream and talus distributions by employing a likelihood ratio approach. Possible distribution sites for each debris slope landform were extracted by applying a spatial integration model, in which we combined fuzzy set model, Bayesian predictive model, and logistic regression model. Moreover, to verify model performance, a success rate curve was prepared by cross-validation. The results showed that elevation, slope, curvature, topographic wetness index, geology, soil drainage, and soil depth were closely related to the debris slope landform sites. In addition, all spatial integration models displayed an accuracy of over 90%. The accuracy of the distribution potential area map of the block stream was highest in the logistic regression model (93.79%). Eventually, the accuracy of the distribution potential area map of the talus was also highest in the logistic regression model (97.02%). We expect that the present results will provide essential data and propose methodologies to improve the performance of efficient and systematic micro-landform studies. Moreover, our research will potentially help to enhance field research and topographic resource management.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.3
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• pp.587-594
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• 2005

In the paper, after we propose a viterbi decoder which has multiple buffering and parallel processing decoding scheme through expanding time-divided imput signal, and map a FPGA, we implement a channel coding system together with PC-based software. Continuous input signal is buffered as order of decoding length and is parallel decoded using a high speed cell for viterbi decoding. Output data rate increases linearly with the cell formed the viterbi decoder, and flexible operation can be satisfied by programming controller and modifying input buffer. The tell for viterbi decoder consists of HD block for calculating hamming distance, CM block for calculating value in each state, TB block for trace-back operation, and LIFO. The implemented cell of viterbi decoder used 351 LAB(Logic Arrary Block) and stably operated in maximum 139MHz in APEX20KC EP20K600CB652-7 FPGA of ALTERA. The whole viterbi decoder including viterbi decoding cells, input/output buffers, and a controller occupied the hardware resource of $23\%$ and has the output data rate of 1Gbps.