• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.305-308
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• 2002

An 1.8V 6bit IGSPS ADC for high speed data acquisition is discussed in this paper. This ADC is based on a flash ADC architecture because the flash ADC is the only practical architecture at conversion rates of IGSPS and beyond. A straightforward 6bit full flash A/D converter consists of two resistive ladders with 63 laps, 63 comparators and digital blocks. One important source of errors in flash A/D converter is caused by the capacitive feedthrough of the high frequency input signal to the resistive reference-lauder. Consequently. the voltage at each tap of the ladder network can change its nominal DC value. This means large transistors have a large parasitic capacitance. Therefore, a dual resistive ladder with capacitor is employed to fix the DC value. Each resistive ladder generates 32 clean reference voltages which alternates with each other. And a two-stage amplifier is also used to reduce the effect of the capacitive feedthrough by minimizing the size of MOS connected to reference voltage. The proposed ADC is based on 0.18${\mu}{\textrm}{m}$ 1-poly 6-metal n-well CMOS technology, and it consumes 307㎽ at 1.8V power supply.

• Smart Structures and Systems
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• v.18 no.2
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• pp.335-354
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• 2016

This contribution presents an extended one-dimensional theory for piezoelectric beam-type structures with non-ideal electrodes. For these types of electrodes the equipotential area condition is not satisfied. The main motivation of our research is originated from passive vibration control: when an elastic structure is covered by several piezoelectric patches that are linked via resistances and inductances, vibrational energy is efficiently dissipated if the electric network is properly designed. Assuming infinitely small piezoelectric patches that are connected by an infinite number of electrical, in particular resistive and inductive elements, one obtains the Telegrapher's equation for the voltage across the piezoelectric transducer. Embedding this outcome into the framework of Bernoulli-Euler, the final equations are coupled to the wave equations for the longitudinal motion of a bar and to the partial differential equations for the lateral motion of the beam. We present results for the wave propagation of a longitudinal bar for several types of electrode properties. The frequency spectra are computed (phase angle, wave number, wave speed), which point out the effect of resistive and inductive electrodes on wave characteristics. Our results show that electrical damping due to the resistivity of the electrodes is different from internal (=strain velocity dependent) or external (=velocity dependent) mechanical damping. Finally, results are presented, when the structure is excited by a harmonic single force, yielding that resistive-inductive electrodes are suitable candidates for passive vibration control that might be of great interest for practical applications in the future.

• ETRI Journal
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• v.30 no.6
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• pp.783-789
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• 2008

A bio-inspired vision chip for edge detection was fabricated using 0.35 ${\mu}m$ double-poly four-metal complementary metal-oxide-semiconductor technology. It mimics the edge detection mechanism of a biological retina. This type of vision chip offer several advantages including compact size, high speed, and dense system integration. Low resolution and relatively high power consumption are common limitations of these chips because of their complex circuit structure. We have tried to overcome these problems by rearranging and simplifying their circuits. A vision chip of $160{\times}120$ pixels has been fabricated in $5{\times}5\;mm^2$ silicon die. It shows less than 10 mW of power consumption.

• Progress in Superconductivity
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• v.5 no.2
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• pp.128-131
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• 2004

The resistive superconducting fault current limiters (SFCLs) are very attractive devices for the electric power network. But they have some serious problems when the YBCO thin films were used for the current limiting materials due to the in homogeneities caused by manufacturing process. When the YBCO films have some inhomogeneities, simultaneous quenches are difficult to achieve when the fault current limiting units are connected in series for increasing operating voltage ratings. Magnetic field application is one of the prospective way of inducing simultaneous quenches far the series-connected resistive FCL components. Magnetic field was typically generated by the fault current thorough a coil, which is connected to components of the fault current limiter in series, leaving the problem, which provides significant inductance to the power line and suppresses critical current density of the superconducting components. In this article we investigated the possible application of the protective current transformer (p-CT), which is available current source to the magnetic coil. This system inductively coupled to the circuit, therefore, remarkably reducing impedance to the circuit. The current by the protective current transformer was directly fed to the coil, generating magnetic field large enough to reduce critical current density of the components. This successfully induced simultaneous quenches of the series-connected resistive FCL components.

• Journal of Korea Society of Digital Industry and Information Management
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• v.20 no.2
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• pp.63-74
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• 2024

This Paper presents a resistive wideband fully differential low-noise amplifier (LNA) designed using a noise-cancellation technique for TV tuner applications. The front-end of the LNA employs a cascode common-gate (CG) configuration, and cross-coupled local feedback is employed between the CG and common-source (CS) stages. The moderate gain at the source of the cascode transistor in the CS stage is utilized to boost the transconductance of the cascode CG stage. This produces higher gain and lower noise figure (NF) than a conventional LNA with inductor. The NF can be further optimized by adjusting the local open-loop gain, thereby distributing the power consumption among the transistors and resistors. Finally, an optimized DC gain is obtained by designing the output resistive network. The proposed LNA, designed in SK Hynix 180 nm CMOS, exhibits improved linearity with a voltage gain of 10.7 dB, and minimum NF of 1.6-1.9 dB over a signal bandwidth of 40 MHz to 1 GHz.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.38 no.2
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• pp.144-150
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• 1989

The competitive power extraction problem in a linear n-port network consisting of resistances and independent sources with the same frequency is solved. For solving the problem, the definition of the two-port image impedances is extended to the n-port image impedances. In a competitive power extraction from an n-port network, the load resistances eventually approach the image resistances been found to be between the reciprocal of the short circuit conductance and the open circuit resistance.

• Journal of Sensor Science and Technology
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• v.17 no.1
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• pp.15-22
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• 2008

When designing image sensors including a CMOS vision chip for edge detection, resolution is a significant factor to evaluate the performance. It is hard to improve the resolution of a bio-inspired CMOS vision using a resistive network because the vision chip contains many circuits such as a resistive network and several signal processing circuits as well as photocircuits of general image sensors such as CMOS image sensor (CIS). Low resolution restricts the use of the application systems. In this paper, we improve the resolution through layout and circuit optimization. Furthermore, we have designed a printed circuit board using FPGA which controls the vision chip. The vision chip for edge detection has been designed and fabricated by using $0.35{\mu}m$ double-poly four-metal CMOS technology, and its output characteristics have been investigated.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.11
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• pp.1098-1103
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• 2013

A low-noise amplifier(LNA) using series RLC matching network and resistive feedback at 8 GHz is presented. Inductive degeneration is used for the input matching with which the proposed LNA shows quite a wide bandwidth in terms of $S_{21}$. An equivalent circuit model is deduced for input matching by conversion from parallel circuit to series resonant circuit. By exploiting the resistive feedback and series RLC input matching, fully integrated LNA achieves maximum $S_{21}$ of 8.5 dB(peak to -3 dB bandwidth is about 3.5 GHz) noise figure of 5.9 dB, and IIP3 of 1.6 dBm while consuming 7 mA from 1.2 V supply.

• Progress in Superconductivity
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• v.7 no.2
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• pp.114-119
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• 2006

High critical current density, high n value, multiple faults endurances, and fast recovery characteristics of YBCO thin films are very attractive characteristics for developing resistive type superconducting fault current limiters. But due to the limited current and voltage ratings of one YBCO module, it is needed to construct series and parallel module connections for high capacity electric networks. Especially for distribution network, more than 30 units should be connected in series to meet voltage level. So in order to construct distribution-level superconducting fault current limiter, simultaneous quench in one YBCO thin films should be realized, and furthermore, quench should be occurred in all fault current limiting units equally to avoid local heating and failures. In this paper, we proposed optimum design of YBCO thin films for fault current limiting module and technical method using shunt resistor to achieve simultaneous quench between multi current limiting units. From the analytical and the experimental results, optimal current path and thickness of shunt material was determined for YBCO thin films and shunt resistor between modules was developed. Finally, 14 kV one phase resistive fault current limiter using multi YBCO thin films was constructed and it was possible to get satisfactory test results.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.4
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• pp.299-312
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• 2006

This paper presents the results of a novel test structure for process control monitor for uncooled IR detector technology of microbolometer arrays. The proposed test structure is based on resistive network configuration. The theoretical model for resistance of this network has been developed using 'Compensation' and 'Superposition' network theorems. The theoretical results of proposed resistive network have been verified by wired hardware testing as well as using an actual 16x16 networked bolometer array. The proposed structure uses simple two-level metal process and is easy to integrate with standard CMOS process line. The proposed structure can imitate the performance of actual fabricated version of area array closely and it uses only 32 pins instead of 512 using conventional method for a $16{\times}16$ array. Further, it has been demonstrated that the defective or faulty elements can be identified vividly using extraction matrix, whose values are quite similar(within the error of 0.1%), which verifies the algorithm in small variation case(${\sim}1%$ variation). For example, an element, intentionally damaged electrically, has been shown to have the difference magnitude much higher than rest of the elements(1.45 a.u. as compared to ${\sim}$ 0.25 a.u. of others), confirming that it is defective. Further, for the devices having non-uniformity ${\leq}$ 10%, both the actual non-uniformity and faults are predicted well. Finally, using our analysis, we have been able to grade(pass or fail) 60 actual devices based on quantitative estimation of non-uniformity ranging from ＜ 5% to ＞ 20%. Additionally, we have been able to identify the number of bad elements ranging from 0 to ＞ 15 in above devices.