• Title/Summary/Keyword: reset time

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Short and Effective Reset Method for AC PDPs

  • Kim, Joon-Yub;Lee, In-Moo
    • 한국정보디스플레이학회:학술대회논문집
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    • 2006.08a
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    • pp.241-245
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    • 2006
  • Reset is necessary for effective addressing in AC PDPs, but reset takes considerable time and produces background luminance. A reset method that takes less time but is effective for addressing is presented. Furthermore, this reset method produces almost negligible background luminance.

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A New Driving Waveform for the Dark Room Contrast Ratio and Reduction of the Reset Period in AC Plasma Display Panel

  • Lee, In-Moo;Kim, Joon-Yub
    • 한국정보디스플레이학회:학술대회논문집
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    • 2005.07b
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    • pp.1183-1186
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    • 2005
  • A new reset method for high contrast ratio and reduction of the reset time is presented. In this new reset method, except the first subfield, a new reset pulse with only ramp-up period is adopted. In this reset method, from the third subfield, the background luminance generated during the reset period is theoretically zero until the first subfield of the following frame. Employing the new reset method, the dark room contrast ratio improved to 3084.7:1 from 189.1:1 of the conventional reset method. The new reset method reduced the required time for reset per subfield to 160us except the first subfield.

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New Driving Method for High Contrast Ratio and Reduction of Reset Period of AC-PDPs

  • Bae, Jeong-Guk;Kim, Joon-Yub
    • 한국정보디스플레이학회:학술대회논문집
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    • 2005.07b
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    • pp.1187-1190
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    • 2005
  • The ramp reset driving method proposed in [1] has been widely adopted because of its stability and high contrast ratio. However, when the conventional ramp reset method is used in PDPs of higher resolution, the long required time for reset often becomes a problem. In this paper, a new driving method that requires much less reset time and that significantly improves the contrast ratio is introduced. Using this new driving method, the required time for reset could be reduced to 150us from 350us of the conventional ramp reset method, and the contrast ratio is almost infinite because the luminance of the off-cell is almost zero.

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A new ramp reset waveform for reducing reset period using address pulse of AC-PDP

  • Kim, Gun-Su;Choi, Hoon-Young;Lee, Seok-Hyun;Kim, Jun-Hyoung;Mim, Byoung-Kuk
    • 한국정보디스플레이학회:학술대회논문집
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    • 2002.08a
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    • pp.609-612
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    • 2002
  • A new reset waveform is proposed for reducing the reset period. A square pulse is applied to the address electrode while reset pulse ramps and before a discharge between the sustain electrodes occurs. The square pulse induces a discharge between the address electrode and the X electrode, and the induced wall charge is opposite to the applied ramp pulse. Thus, the next discharge between the sustain electrodes becomes weaker. The weaker discharge lowers background luminance and improves contrast ratio. Thus, the new reset waveform can reduce ramp up time in the ramp reset waveform The experimental results show that the ramp up time can be reduced by about 90% compared with the conventional ramp reset waveform.

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A PFD (Phase Frequency Detector) with Shortened Reset time scheme (Reset time을 줄인 Phase Frequency Detector)

  • 윤상화;최영식;최혁환;권태하
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2003.10a
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    • pp.385-388
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    • 2003
  • In this paper, a D-Latch is replaced by a memory cell on the proposed PFD to improve response tine by reducing reset me. The PFD has been simulated using HSPICE with a Hynix 0.35um CMOS process to prove the performance improvement.

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A New Method to Reduce Reset Period in AC Plasma Display Panel (AC PDP의 Reset 기간 단축을 위한 새로운 구동방식에 관한 연구)

  • Lee, Sang-Hyeon;Park, Jeong-Hu
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.50 no.10
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    • pp.517-521
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    • 2001
  • The voltage controlled ramp(VCR) waveform has recently been introduced in the reset period prior to addressing for plasma display. However, this method shows the oscillation of gap voltage when the ramp rate is increased in order to reduce reset period. In this paper a current controlled ramp(CCR) waveform method is suggested. This method can suppress the oscillation of gap voltge under the condition of shorter ramp time. Moreover, the reset time can be reduced about 30% compared with VCR method under the same background luminance.

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Improvement of the Contrast Ratio and Reduction of the Reset Period by Current Controlled Ramp Wavefrom

  • Lee, Sung-Hyun;Kim, Dong-Hyun;Park, Chung-Hoo;Shin, Joong-Hong;Yoo, Choong-Hee
    • Journal of Information Display
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    • v.2 no.4
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    • pp.39-45
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    • 2001
  • The voltage controlled ramp(VCR) waveform has recently been introduced in the reset period prior to addressing for plasma display. However, this method results in the oscillation of the gap voltage when the ramp rate is increased so as to reduce reset period. In this paper a current controlled ramp(CCR) waveform method in the reset period is suggested. This method can suppress the oscillation of gap voltage under the condition of shorter ramp time. Moreover, the reset time can be reduced by about 30 % compared with the VCR method under the same background luminance.

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The ADR(Address During Reset) Driving Method for High-Speed Addressing in an AC-PDP (AC PDP에서 고속 어드레싱을 위한 ADR(Address During Reset) 구동 방식)

  • Song Keun-Young;Kim Gun-Su;Lee Seok-Hyun
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.54 no.6
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    • pp.269-273
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    • 2005
  • In order to achieve high efficiency and low cost, new high-speed addressing method is suggested. This can be implemented by reducing the address discharge time lag through the priming effect. This paper suggests a new ADR(Address During Reset) driving method which provides priming particles by a separated driving method without adding auxiliary electrode or auxiliary discharge. The experimental results show an approximately 100ns reduction in the formative delay time of address discharge and a reduction in jitter of over 200ns. Also, due to enough time being available for reset, there was a reduction of about 29$\%$ in linht emitted during the reset period considerably.

Compact Power-on Reset Circuit Using a Switched Capacitor

  • Seong, Kwang-Su
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.14 no.5
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    • pp.625-631
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    • 2014
  • We propose a compact power-on reset circuit consisting of a switched capacitor, a capacitor, and a Schmitt trigger inverter. A switched capacitor working with a clock signal charges the capacitor. Thus, the voltage across the capacitor is increased toward the supply voltage. The circuit provides a reset pulse until the voltage across the capacitor reaches the high threshold voltage of the Schmitt trigger inverter. The proposed circuit is simple, compact, has no static power consumption, and works for a wide range of power-on rising times. Furthermore, the clock signal is available while the reset pulse is activated. The proposed circuit works for up to 6 s of power-on rising time, and occupies a $60{\times}30{\mu}m^2$ active area.

Characteristic of a Negative Driving Waveform in ac PDPs

  • Kang, Jung-Won
    • 한국정보디스플레이학회:학술대회논문집
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    • 2009.10a
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    • pp.97-100
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    • 2009
  • A negative waveform was studied to improve the driving characteristics of reset and address periods in ac PDP. Comparative experiments between negative and conventional positive waveforms were performed with 42-inch XGA PDP module. The negative waveform showed lower breakdown voltage than the conventional positive waveform in reset period. Due to its weak and stable discharge during reset period, the contrast ratio was improved by decreasing the black luminance. During address period, the discharge time-lag was measured. The formative time lag ($=T_f$) of negative waveform was improved about 22.8% than $T_f$ of conventional positive waveform.

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