• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.1191-1192
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• 2011

We released new triple redundant digital excitation system with real time generator-turbine simulator. One of its great merits is the real time generator-turbine simulator when it was compared with the other products. If excitation system is tripped by unexpected faults, Maintenance man can do easily performance test of digital excitation control board, sequence relay and thyristor switching device of phase controlled rectifier without manufacturer's support. For the verification of this system, It was tested with an actual excitation system implemented on 5kVA M-G Set. After finishing the tests, the trial product will be installed and operated at a 500MW thermal power plant.

• Proceedings of the KIEE Conference
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• 2005.05a
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• pp.194-196
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• 2005

The command processor in satellite handles the capability of the process of command transmitted from ground station and deliver the processed data to on board computer in satellite. The command processor is consisted of redundant box to increase the reliability and availability of the capability. At each command processor, the processing time of each command processor is different, so the mismatch of processing time makes it difficult to timely synchronize the reception to on board computer and even will be became worse under the command processor's fault. To minimize the tine loss induced by the command processor's fault on board computer must analyze the time distribution of command propagation. This paper presents the logic of minimizing the delay error of command propagation the logic of analyzing the output of command processor.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.875-878
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• 1998

In this thesis, we present efficient techniques to reduce the switching activity in a CMOS combinational logic network based on local logic transforms. But this techniques is not appropriate in the view of testability because of deteriorating the random pattern testability of a circuit. This thesis proposes a circuit design method having two operation modes. For the sake of power dissipation(normal operation mode), a gate output switches as rarely as possible, implying highly skewed signal probabilities for 1 or 0. On the other hand, at test mode, signals have probabilities of being 1 or 0 approaching 0.5, so it is possible to exact both stuck-at faults on the wire. Therefore, the goals of synthesis for low power and random pattern testability are achieved. The hardware overhead sof proposed design method are only one primary input for mode selection and AND/OR gate for each redundant connection.

• Journal of Power Electronics
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• v.10 no.1
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• pp.34-42
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• 2010

Reliability is an important issue in cascaded H-bridge converters (CHB converters) because they use a high number of power semiconductors. A faulty power cell in a CHB converter can potentially lead to expensive downtime and great losses on the consumer side. With a fault-tolerant control strategy, operation can continue with the undamaged cells; thus increasing the reliability of the system. In this paper, the operating principles and the control method for a CHB multilevel rectifier are introduced. The influence of various faults on the CHB converter is investigated. The method of fault diagnosis and the bypassing of failed cells are explained. A fault-tolerant protection strategy is proposed to achieve redundancy in the CHB rectifier. The redundant H-bridge concept helps to deal with device failures and to increase system reliability. Simulation results verify the performance of the proposed strategy.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.2
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• pp.94-103
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• 1994

In testing for practical scan disigned logic circuits, there may exist logic value constraints on some part of primary inputs due to various requirements on design and test. This paper presents a logic value system called taboo logic values which targets the test pattern generation of logic circuits under logic value constraints. The taboo logic system represents the logic value constraints and identifies additional logic value constraints through the implication of the tqaboo logic values using a taboo logic calculus. Those identified logic value constraints will guide the search during the test pattern generation of avoid the unfruitful searches and to identify redundant faults due to the logic value constraints very quickly. Finally, experimental results on ISCAS85 benchmark circuits will demonstrate the efficiency of the taboo logic values.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.28 no.11
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• pp.1685-1691
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• 2004

This paper describes the fault detection and failsafe logic to be used in an Electronic Stability Program(ESP). The aim of this paper is to prevent of erroneous controls in the ESP. Developed this paper introduces the fault detection logic and evaluation of residual signals. The failsafe logic consists of four redundant sub-models, which can be used for detecting the faults in various sensors (yaw rate, lateral acceleration, steering wheel angle). We present two mathematical residual generation methods : one is a method using the average value and the other is a method using the minimum value of the each residual. We verified a failsafe logic developed using vehicle test results also we compare vehicle model based simulation results with test vehicle results.

• Proceedings of the KSME Conference
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• 2004.04a
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• pp.774-779
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• 2004

This paper describes the fault detection and failsafe logic to be used in the Electronic Stability Program (ESP). The Aim of this paper is prevention of erroneous control in the ESP. This paper introduces the fault detection logic and evaluation of residual signals. Failsafe logic consist of four redundant sub-models and they can be used for the detection of faults in each sensor (yaw rate, lateral acceleration, steering wheel angle). We presents two mathematical residual generation method ; one is the method by the average value, and the other is the method by the minimum value of the each residual. We verify a failsafe logic using vehicle test results, also we compare vehicle model based simulation results with test vehicle results.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.6
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• pp.1169-1181
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• 1994

The Gamma Network contains the redundant path thereby is provides the ability to tolerate the faults occured. However, in case of identical the source and destination number, only a single path exists, therefore there is no way of connecting for the fault situation. In addition, for the dynamic packet routing strategy, it shoed perform backtracking analysis to find the redundant path. In this paper we proposed a new network, Dual Network, to resolve these drawbacks. The Dual Network uses switching elements about the same network size as the Gamma Network except first and last stage, and it is more efficient than the Gamma Network, for it has reduced the switching stage by one. And since is used a destination tag routing scheme for the control algorithm, it has on advantage of becoming of simpler and faster routing control.

• Korean Journal of Computational Design and Engineering
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• v.17 no.2
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• pp.97-110
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• 2012

High performance sensors and modern data logging technology with real-time telemetry facilitate system fault diagnosis in a very precise manner. Fault detection, isolation and identification in fault diagnosis systems are typical steps to analyze the root cause of failures. This systematic failure analysis provides not only useful clues to rectify the abnormal behaviors of a system, but also key information to redesign the current system for retrofit. The main barriers to effective failure analysis are: (i) the gathered data (event) logs are too large in general, and further (ii) they usually contain noise and redundant data that make precise analysis difficult. This paper therefore applies suitable pre-processing techniques to data reduction and feature extraction, and then converts the reduced data log into a new format of event sequence information. Finally the event sequence information is decoded to investigate the correlation between specific event patterns and various system faults. The efficiency of the developed pre-filtering procedure is examined with a terminal box data log of a marine diesel engine.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.3 no.3
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• pp.51-61
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• 2010

Nowadays, there are various networked systems with many computers. In most networked systems, a crucial objective is to keep transmitting and/or receiving data continuously even though failures exist. How can one make a computer continue transmitting and/or receiving data even when there are some errors on a link? Fault-Tolerant Ethernet (FTE) can be a solution to this question. In this paper, we propose a Localized Software-based Fault-Tolerant Ethernet (LSFTE). Our new approach fulfills the general FTE requirements. It takes advantage of redundant cable lines to maintain communication in a faulty environment. A software layer, which uses a simple and effective algorithm, is added above the LAN card driver software to detect and overcome faults. For our approach, there is no need to change the existing hardware or the end-use interfaces. Furthermore, the fault-detection time is reduced significantly compared to the conventional software-based approach.