• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 하계종합학술대회논문집
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• pp.823-826
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• 1998

This paper addresses a characterization of fault effects in asynchronous circuits. A characterization has been performed on races caused by a single stuck-at faults (SSAF). The faults sometimes lead to races in faulty circuits, which prevent faults from observing and the circuit is insufficiently tested. To identify those obstacles, we have proposed non-detectable single stuck-at fault(NDSSAF) conditions and proposed an algorithm to find them. In the help of the proposed methodology, the asynchronous circuits can be fully SSAF testable.

• 제어로봇시스템학회논문지
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• 제17권11호
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• pp.1067-1073
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• 2011

In this paper, the methodology of a CA (Control Allocation) based FTNCS (Fault-Tolerant Networked Control System) is proposed. Control allocation is a control surface management technique by redistributing the redundant control surfaces in overactuated systems. In modern high performance aircrafts, they adopt many redundant control surfaces to provide high performance and to satisfy various tactical requirements. Moreover, redundant control surfaces provide an opportunity to compensate performance degradation due to failures in more than one actuator by re-allocating redundant control surfaces. Simulation results with an F-18 HARV demonstrate that the proposed CA based FTNCS can achieve a fast and accurate tracking performance even in the presence of actuator faults.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2003년도 ICCAS
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• pp.2576-2581
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• 2003

We consider fault detection and isolation (FDI) problem for inertial navigation systems (INS) which use redundant inertial sensors and propose an FDI method using average of multiple parity vectors which reduce false alarm and wrong isolation, and improve correct isolation. We suggest optimal isolation threshold based on navigation performance, and suggest optimal sample number to obtain short detection time and to enhance detectability of faults little larger than threshold.

• 한국조명전기설비학회:학술대회논문집
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• 한국조명전기설비학회 1999년도 학술대회논문집-국제 전기방전 및 플라즈마 심포지엄 Proceedings of 1999 KIIEE Annual Conference-International Symposium of Electrical Discharge and Plasma
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• pp.267-272
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• 1999

In many fields of automation, increasingly high demands are being placed on the availability and fault tolerance of programmable logic controller(PLC). Particularly in fields where a plant shutdown would be extremely expensive. In such cases, only redundant systems can offer the standard of availability required. The redundant configurations contain more then would normally be necessary for the relevant function. Fault tolerant systems will normally continue to operate even if one or more faults cause parts of the control system to fail.

• 전기학회논문지
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• 제63권1호
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• pp.70-75
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• 2014

TMR(triple modular redundant) digital excitation system with simulator is developed for tuning optimal control parameters during commissioning test and coping with system faults rapidly. A new system which mocks up virtual generator, turbine, grid can simulate as if excitation system is connected to a real generator system by setting four switches. The maintenance crew using the simulator is able to test perfectly the phase controller rectifiers, field breaker, sequence relays as well as TMR controller of the excitation system. Commissioning and performance results about the excitation system with simulator is discussed. The trial product was installed and operated at a 500MW thermal power plant after the commissioning test.

• 한국통신학회논문지
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• 제27권1C호
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• pp.96-102
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• 2002

전류 테스팅은 전류 테스팅은 CMOS 회로의 합선고장을 효과적으로 검출할 수 있는 기법이다. 그러나 합선고장의 복잡도가 O($n^2$)이고, 또한 전류 테스트 방식이 전압 테스트 방식에 비해서 상대적으로 긴 테스트 시간이 필요하기 때문에 두 합선된 노드가 항상 같은 값을 가지는 노드를 찾아내어 제거하는 효율적인 무해고장 검출기법이 필요하다. 이러한 무해고장은 보다 정확한 고장 검출율을 위해서 ATPG 툴을 이용하여 검출될 수 있어야 한다. 본 논문에서는 효율적인 전류 테스트를 위한 객체 기반의 무해고장 검출기법을 제안한다. ISCAS 벤치마크 회로에 대한 실험을 통해서 제안된 기법이 기존의 다른 방식보다 더 효과적임을 보여주었다.

• 전자공학회논문지C
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• 제34C권8호
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• pp.39-48
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• 1997

The fast redundancy identification is required to perform an efficient test pattern genration. Due to the reconvergent fanouts which make the dependency among objectives and the fault propagation blocking, there may exist redundnat faults in the cirucit. This paper presents the isomorphism identification and the pseudo dominator algorithms which are useful to identify redundant faults in combinational circuits. The isomorphism identification algorithm determines whether mandatory objectives required for fault detection cannot be simultaneously satisfied from primary input assignments or not using binary decision diagrma. The pseudo dominator algorithm determines whether faults propagation is possible or not by considering all paths at a given fanout node. Several experiments using ISCAS 85 benchmark circuits demonstrate the efficiency and practicability of the algorithms.

• 제어로봇시스템학회논문지
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• 제19권4호
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• pp.328-333
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• 2013

Since a slight malfunction of control systems in a nuclear power plant may cause huge catastrophes, such control systems usually have multiple redundancy and reliable features, and their reliability and availability should be analyzed and verified thoroughly. This paper performed the reliability analysis of the SPLC (Safety Programmable Logic Controller) that is under developed as the control systems for the next generation nuclear power plant. One of the key features of SPLC is that it has multiple redundancy modes as faults happen, which means the reliability analysis for one fixed redundant model is not enough to analyze the reliability of SPLC. With considering this reconfigurable concept, FTA (Fault Tree Analysis) was used to capture fault-relationship among sub-modules. The analysis results show that MTTF (Mean Time to Fault) of SPLC is 45,080 hours, which is a about 4.5 times longer than the regulation, 10,000 hours.

• 한국신뢰성학회:학술대회논문집
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• 한국신뢰성학회 2000년도 춘계학술대회 발표논문집
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• pp.231-238
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• 2000

The distributed digital control system has many shared common components, and a single fault in the system may have effects on not a single function. Not as in an analog system, the faults in a digital system usually make discrete and abrupt changes in its output, which are hard to be expected. To cope with these situations, the fault-tolerance is an inevitable property of a distributed control system. A distributed digital control system consists of many equipments, and each equipment can be implemented by many different technologies. The fault-tolerance has to be implemented depend-ing on the overall architecture and how each equipment is implemented. The paper analyzes and compares the strategies and tactics to add the fault-tolerances in a distributed digital control system, and studies how they can be combined appropriately.

• 제어로봇시스템학회논문지
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• 제14권4호
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• pp.376-380
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• 2008

This paper deals with a performance analysis of real-time control systems, which engages DMR(dual modular redundancy) to detect transient errors and checkpointing technique to tolerate transient errors. Transient errors are caused by transient faults and the most significant type of errors in reliable computer systems. Transient faults are assumed to occur according to a Poisson process and to be detected by a dual modular redundant structure. In addition, an equidistant checkpointing strategy is considered. The probability of the successful task completion in a real-time control system where periodic checkpointing operations are performed during the execution of a real-time control task is derived. Numerical examples show how checkpoiniting scheme influences the probability of task completion. In addition, the result of the analysis is compared with the simulation result.