• Current Photovoltaic Research
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• v.3 no.4
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• pp.130-134
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• 2015

The high efficiency cell research processes through the KF post deposition treatment (PDT) of the $Cu(In,Ga)Se_2(CIGS)$ thin film has been very actively progress. In this study, it CIGS thin film deposition process when KF PDT 300 to the processing temperature, 350, $400^{\circ}C$ changed to soda-lime glass (SLG) efficiency of the CIGS thin film characteristics, and solar cell according to Na presence of diffusion from the substrate the effects were analyzed. As a result, the lower the temperature of KF PDT and serves to interrupt the flow of current K-CIGS layer is not removed from the reaction surface, FF and photocurrent is decreased significantly. Blocking of the Na diffusion from the glass substrate is significantly increased while the optical voltage, photocurrent and FF is a low temperature (300, $350^{\circ}C$) in the greatly reduced, and in $400^{\circ}C$ tend to reduce fine. It is the presence of Na in CIGS thin film by electron-induced degradation of the microstructure of CIGS thin film is expected to have a significant impact on increasing the hole recombination rate a reaction layer is formed of the K elements in the CIGS thin film surface.

• Journal of Sensor Science and Technology
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• v.5 no.5
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• pp.1-10
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• 1996

Solar cells made of the edge-defined film-fed growth Si are characterized using current-voltage, surface photovoltage, electron beam induced current, electron microprobe, scanning electron microscopy, and electron backscattering. The weak temperature dependence of the I-V curves in the EFG solar cells is due to a voltage variable shunt resistance giving higher diode ideality factors than the ideal one. The voltage variable shunt resistance is modeled by a modified recombination mechanism which includes carrier tunneling to distributed impurity energy states in the band gap within the space-charge region. The junction integrity and the substrate quality are characterized simultaneously by combining I-V and surface photovoltage (SPV) measurements. The diode ideality factors and the surface photovoltages characterize the junction integrity while the SPV diffusion lengths characterizes the substrate quality. Most of the measured samples show the voltage variable shunt resistance although how serious it is depends on the solar cell efficiency. The voltage variable shunt resistance is understood as one of the most important factors of the degradation of EFG solar cells.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.3
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• pp.827-834
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• 2010

We have performed numerical simulations of the electrical characteristics for multi-layer organic light emitting diode devices with doped emitting layer using a commercial simulation program. In this paper, the basic structure consists of the ITO/NPB/$Alq_3$:C545T(%)/$Alq_3$/LiF/Al, four devices that were composed of $Alq_3$ as the host and C545T as the green dopant with different concentration, were studied. As the result, the variations of the doping concentration rate of C545T have a effect on the voltage-current density characteristics. The voltage-current characteristics are quite consistent with the results which were experimentally determined in a previous reference paper. In addition, the voltage-luminance characteristics were greatly improved, and the luminous efficiency was improved three times. In order to analyze these driving mechanism, we have investigated the distribution of electric field, charge density of the carriers, and recombination rates in the inner of the OLED devices.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.292-295
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• 2004

The SIT was introduced by Nishizawa. in 1972. When compared with high-voltage, power bipolar junction transistors, SITs have several advantages as power switching devices. They have a higher input impedance than do bipolar transistors and a negative temperature coefficient for the drain current that prevents thermal runaway, thus allowing the coupling of many devices in parallel to increase the current handling capability. Furthermore, the SIT is majority carrier device with a higher inherent switching speed because of the absence of minority carrier recombination, which limits the speed of bipolar transistors. This also eliminates the stringent lifetime control requirements that are essential during the fabrication of high-speed bipolar transistors. This results in a much larger safe operating area(SOA) in comparison to bipolar transistors. In this paper, vertical SIT structures are proposed to improve their electrical characteristics including the blocking voltage. Besides, the two dimensional numerical simulations were carried out using ISE-TCAD to verify the validity of the device and examine the electrical characteristics. A trench gate region oxide power SIT device is proposed to improve forward blocking characteristics. The proposed devices have superior electrical characteristics when compared to conventional device. Consequently, the fabrication of trench oxide power SIT with superior stability and electrical characteristics is simplified.

• Current Photovoltaic Research
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• v.9 no.3
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• pp.84-95
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• 2021

The power conversion efficiency of Cu₂ZnSnSe₄ (CZTSe) solar cells depends on the absorber layer thickness; however, changes in the characteristics of the cells with varying absorber layer thickness are unclear. In this study, we investigated the changes in the characteristics of CZTSe solar cells for varying absorber layer thickness. Five absorber thicknesses were employed: CZTSe1 2.78 ㎛, CZTSe2 1.01 ㎛, CZTSe3 0.55 ㎛, CZTSe4 0.29 ㎛, and CZTSe5 0.15-0.23 ㎛. The efficiency of the CZTSe solar cells decreased as the absorber thickness decreased, resulting in power conversion efficiencies of 10.45% (CZTSe1), 8.67% (CZTSe2), 7.14% (CZTSe3), 3.44% (CZTSe4), and 1.54% (CZTSe5). As the thickness of the CZTSe absorber layer decreased, the electron-hole recombination at the grain boundaries and the absorber-back-contact interface increased. This caused an increase in the current loss, owing to light loss in the long-wavelength region. In addition, as the thickness of the CZTSe absorber layer decreased, more ZnSe was produced, and the resulting defects and defect clusters led to an open-circuit voltage loss.

• Journal of the Korean Vacuum Society
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• v.12 no.4
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• pp.239-250
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• 2003

The reliability degradation phenomena in the SiGe hetero-junction bipolar transistor (HBT) are investigated in this review. In the case of the SiGe HBT the decrease of the current gain, the degradation of the AC characteristics, and the offset voltage are frequently observed, which are attributed to the emitter-base reverse bias voltage stress, the transient enhanced diffusion, and the deterioration of the base-collector junction due to the fluctuation in fabrication process, respectively. The reverse-bias stress on the emitter-base junction causes the recombination current to rise, increasing the base current and degrading the current gain, because hot carriers formed by the high electric field at the junction periphery generate charged traps at the silicon-oxide interface and within the oxide region. Because of the enhanced diffusion of the dopants in the intrinsic base induced by the extrinsic base implantation, the shorter distance between the emitter-base junction and the extrinsic base than a critical measure leads to the reduction of the cut-off frequency ($f_t$) of the device. If the energy of the extrinsic base implantation is insufficient, the turn-on voltage of the collector-base junction becomes low, in the result, the offset voltage appears on the current-voltage curve.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.404-404
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• 2016

태양전지 제작 시 표면에 피라미드 구조를 형성하면 입사되는 광의 흡수를 높여 광 생성 전류의 향상에 기여한다. 일반적인 KOH를 이용한 습식 표면조직화 공정은 평균 10%의 반사율을 보였으며, 유도 결합 플라즈마를 이용한 RIE 공정은 평균 5.4%의 더 낮은 반사율을 보였다. 그러나 RIE 공정을 이용한 표면조직화는 낮은 반사율과 서브 마이크론 크기의 표면 구조를 만들 수 있지만 플라즈마 조사에 의한 표면 손상이 많이 발생하게 된다. 이러한 표면 손상은 태양전지 제작 시 표면에서 높은 재결합 영역으로 작용하게 되어 포화 전류(saturation currents, $J_0$)를 증가시키고 캐리어 수명(carrier lifetime, ${\tau}$)을 낮추는 결함 요소로 작용한다. 이러한 플라즈마에 의한 표면 손상을 제거하기 위해 HF, HNO3, DI-water를 이용하여 DRE(Damage Remove Etching) 공정을 진행하였다. DRE 공정은 HF : DI-water 솔루션과 HNO3 : HF : DI-water 솔루션의 두 가지 공정을 이용하여 공정 시간을 가변하며 진행하였다. 포화전류($J_0$), 캐리어 수명(${\tau}$), 벌크 캐리어 수명(Bulk ${\tau}$)을 비교를 하기위해 KOH, RIE, RIE + DRE 공정을 진행한 세 가지 샘플로 실험을 진행하였다. DRE 공정을 적용할 경우 공정 시간이 지날수록 반사도가 높아지는 경향을 보였지만, 두 번째의 최적화된 솔루션 공정에서 $2.36E-13A/cm^2$, $42{\mu}s$의 $J_0$, Bulk ${\tau}$값과 가장 높은 $26.4{\mu}s$의 ${\tau}$를 얻을 수 있었다. 이러한 결과는 오제 재결합(auger recombination)이 가장 많이 발생하는 지역인 표면과 불균일한 도핑 영역에서 DRE 공정을 통해 나아진 표면 특성과 균일한 도핑 프로파일을 형성하게 되어 재결합 영역과 $J_0$가 감소 된 것으로 판단된다. 높아진 반사도의 경우 $SiN_x$를 이용한 반사방지막을 통해 표면 반사율을 1% 이내로 내릴 수 있어 보완이 가능하였다. 본 연구에서는 RIE 공정 중 플라즈마에 의해 발생하는 표면 손상 제거를 통하여 캐리어 라이프 타임의 향상된 조건을 찾기 위한 연구를 진행하였으며, 기존 RIE 공정에 비해 반사도의 상승은 있지만 플라즈마로 인한 표면 손상을 제거하여 오제 재결합에 의한 발생하는 $J_0$를 낮출 수 있었고 높은 ${\tau}$값인 $26.4{\mu}s$의 결과를 얻어 추후 태양전지 제작에 향상된 효율을 기대할 수 있을 것으로 기대된다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.3 no.1
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• pp.18-25
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• 1978

The 1/f noise spectrum of short-circuited output drain current due to the Shockley-Read-Hal] recombination centers with a single lifetime in homogeneous nondegenerate MOS-field effcte transtors with n-type channel is calculated under the assumptions that the quasi-Fermi level for the carriers in each energy band can not be defined if we include the fluctuation for time varying quantities. and so 1/f noise is a majority carrier effect. Under these assumptions the derived 1/f noise in this paper show some essential features of the 1/f noise in MOS-field effect transistors. That is, it has no lowfrequency plateau and is proportionnal to the channel cross area A and to the driain bias voltage Vd and inversely proportional to the channel length L3 in MOS field effect transistors. This model can explain the discrepancy between the transition frequency of the noise spectrum from 1/f- response to 1/f2 and the frequency corresponding to the relaxation time related to the surface centers in p-n junction diodes. In this paper the results show that the functional form of noise spectrum is greatly influenced by the functional forms of the electron capture probability cn (E) and the relaxation time r (E) for scattering and the case of lattice scattering show to be responsible for the 4 noise in MOS fold effect transistors. So we canconclude that the source of 1/f noise is due to lattice scattering.

• Solar Energy
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• v.17 no.4
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• pp.3-11
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• 1997

Because grain boundaries in polycrystalline silicon act as potential barriers and recombination centers for the photo-generated charge carriers, these defects degrade conversion effiency of solar cell. To reduce these effects of grain boundaries, we investigated various influencing factors such as thermal treatment, various grid pattern, selective wet etching for grain boundaries, buried contact metallization along grain boundaries, grid on metallic thin film. Pretreatment above $900^{\circ}C$ in $N_2$ atmosphere, gettering by $POCl_3$ and Al treatment for back surface field contributed to obtain a high quality poly-Si. To prevent carrier losses at the grain boundaries, we carried out surface treatment using Schimmel etchant. This etchant delineated grain boundaries of $10{\mu}m$ depth as well as surface texturing effect. A metal AI diffusion into grain boundaries on rear side reduced back surface recombination effects at grain boundaries. A combination of fine grid with finger spacing of 0.4mm and buried electrode along grain boundaries improved short circuit current density of solar cell. A ultra-thin Chromium layer of 20nm with transmittance of 80% reduced series resistance. This paper focused on the grain boundary effect for terrestrial applications of solar cells with low cost, large area, and high efficiency.

• Korean Journal of Materials Research
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• v.3 no.2
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• pp.121-130
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• 1993

The GaP crystals were grown by synthesis solute diffusion method and its properties were investigated. High quality single crystals were obtained by pull-down the crystal growing ampoule with velocity of 1.75mm/day. Etch pits density along vertical direction of ingot was increased from 3.8 ${\times}{10^4}$c$m^{-2}$ of the first freeze to 2.3 ${\times}{10^5}$c$m^2$ of the last freeze part. The carrier concentration and mobilities at room temperature were measured to 197.49cc$m^2$/V.sec and 6.75 ${\times}{10^{15}}$c$m^{-3]$, respectively. The temperature dependence of optical energy gap was empirically fitted to $E_g$(T)=[2.3383-(6.082${\times}{10^{-4}}$)$T^2$/(373. 096+TJeV. Photoluminescence spectra measured at low temperature were consist with sharp line-spectra near band-gap energy due to bound-exciton and phonon participation in band edge recombination process. Zn-diffusion depth in GaP was increased with square root of diffusion time and temperature dependence of diffusion coefficient was D(Tl = 3.2 ${\times}{10^3}$exp( - 3.486/$k_{\theta}$T)c$m^2$/sec. Electroluminescence spectra of p-n GaP homojunction diode are consisted with emission at 630nm due to recombination of donor in Zn-O complex center with shallow acceptors and near band edge emission at 550nm. Photon emission at current injection level of lower than 100m A was due to the band-filling mechanism.