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Degradation from Polishing Damage in Ferroelectric Characteristics of BLT Capacitor Fabricated by Chemical Mechanical Polishing Process (화학적기계적연마 공정으로 제조한 BLT Capacitor의 Polishing Damage에 의한 강유전 특성 열화)

  • Na, Han-Yong;Park, Ju-Sun;Jung, Pan-Gum;Ko, Pil-Ju;Kim, Nam-Hoon;Lee, Woo-Sun
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2008.06a
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    • pp.236-236
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    • 2008
  • (Bi,La)$Ti_3O_{12}$(BLT) thin film is one of the most attractive materials for ferroelectric random access memory (FRAM) applications due to its some excellent properties such as high fatigue endurance, low processing temperature, and large remanent polarization [1-2]. The authors firstly investigated and reported the damascene process of chemical mechanical polishing (CMP) for BLT thin film capacitor on behalf of plasma etching process for fabrication of FRAM [3]. CMP process could prepare the BLT capacitors with the superior process efficiency to the plasma etching process without the well-known problems such as plasma damages and sloped sidewall, which was enough to apply to the fabrication of FRAM [2]. BLT-CMP characteristics showed the typical oxide-CMP characteristics which were related in both pressure and velocity according to Preston's equation and Hernandez's power law [2-4]. Good surface roughness was also obtained for the densification of multilevel memory structure by CMP process [3]. The well prepared BLT capacitors fabricated by CMP process should have the sufficient ferroelectric properties for FRAM; therefore, in this study the electrical properties of the BLT capacitor fabricated by CMP process were analyzed with the process parameters. Especially, the effects of CMP pressure, which had mainly affected the removal rate of BLT thin films [2], on the electrical properties were investigated. In order to check the influences of the pressure in eMP process on the ferroelectric properties of BLT thin films, the electrical test of the BLT capacitors was performed. The polarization-voltage (P-V) characteristics show a decreased the remanent polarization (Pr) value when CMP process was performed with the high pressure. The shape of the hysteresis loop is close to typical loop of BLT thin films in case of the specimen after CMP process with the pressures of 4.9 kPa; however, the shape of the hysteresis loop is not saturated due to high leakage current caused by structural and/or chemical damages in case of the specimen after CMP process with the pressures of 29.4 kPa. The leakage current density obtained with positive bias is one order lower than that with negative bias in case of 29.4 kPa, which was one or two order higher than in case of 4.9 kPa. The high pressure condition was not suitable for the damascene process of BLT thin films due to the defects in electrical properties although the better efficiency of process. by higher removal rate of BLT thin films was obtained with the high pressure of 29.4 kPa in the previous study [2].

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Spatial dispersion of aggregate in concrete a computer simulation study

  • Hu, Jing;Chen, Huisu;Stroeven, Piet
    • Computers and Concrete
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    • v.3 no.5
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    • pp.301-312
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    • 2006
  • Experimental research revealed that the spatial dispersion of aggregate grains exerts pronounced influences on the mechanical and durability properties of concrete. Therefore, insight into this phenomenon is of paramount importance. Experimental approaches do not provide direct access to three-dimensional spacing information in concrete, however. Contrarily, simulation approaches are mostly deficient in generating packing systems of aggregate grains with sufficient density. This paper therefore employs a dynamic simulation system (with the acronym SPACE), allowing the generation of dense random packing of grains, representative for concrete aggregates. This paper studies by means of SPACE packing structures of aggregates with a Fuller type of size distribution, generally accepted as a suitable approximation for actual aggregate systems. Mean free spacing $\bar{\lambda}$, mean nearest neighbour distance (NND) between grain centres $\bar{\Delta}_3$, and the probability density function of ${\Delta}_3$ are used to characterize the spatial dispersion of aggregate grains in model concretes. Influences on these spacing parameters are studied of volume fraction and the size range of aggregate grains. The values of these descriptors are estimated by means of stereological tools, whereupon the calculation results are compared with measurements. The simulation results indicate that the size range of aggregate grains has a more pronounced influence on the spacing parameters than exerted by the volume fraction of aggregate. At relatively high volume density of aggregates, as met in the present cases, theoretical and experimental values are found quite similar. The mean free spacing is known to be independent of the actual dispersion characteristics (Underwood 1968); it is a structural parameter governed by material composition. Moreover, scatter of the mean free spacing among the serial sections of the model concrete in the simulation study is relatively small, demonstrating the sample size to be representative for composition homogeneity of aggregate grains. The distribution of ${\Delta}_3$ observed in this study is markedly skew, indicating a concentration of relatively small values of ${\Delta}_3$. The estimate of the size of the representative volume element (RVE) for configuration homogeneity based on NND exceeds by one order of magnitude the estimate for structure-insensitive properties. This is in accordance with predictions of Brown (1965) for composition and configuration homogeneity (corresponding to structure-insensitive and structure-sensitive properties) of conglomerates.

The Accelerated Life Test of 2.5 Inch Hard Disk In The Environment of PC using (PC 사용 환경의 2.5 인치 하드디스크의 가속 수명 시험)

  • Cho, Euy-Hyun;Park, Jeong-Kyu;Seo, Hui-Don
    • Journal of Digital Contents Society
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    • v.15 no.1
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    • pp.19-27
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    • 2014
  • In order to estimate the life of 2,5 inch HDD which is adopted by PC environment, make the test plan which reflect the failure mode of market, make the test model of accelerated life test which reflect the stress of temperature. after an analysis of the environment of PC using, test procedure was decided that operation was write 50 % and read 50 %, and then access method was sequential 50 % and random 50%. The acceleration life test was executed on condition that temperature was $50^{\circ}C$ and $60^{\circ}C$, performance was 95 % in max performance, test time was 1000 hours. by the test of goodness of fit of anderson-darling of the failure data during test, it was confirmed that the distribution of failure fellow weibull. test for shape and scale was equal, and shape parameter was 0.7177, characteristic life was 429434 hours at normal user condition($30^{\circ}C$) by the analysis of weibull-arrhenius modeling. It made no difference about the statistics when equality test was executed. The activation energy was 0.2775eV. In analyzing between the failure samples of acceleration test and the samples of market return even though there is detail difference about the share of failure mode, the rank of share was almost same. This study suggest the test procedure of acceleration test of 2.5 inch HDD in PC using environment, and help the life estimation at manufacture and user.

DEVELOPMENT OF THE READOUT CONTROLLER FOR INFRARED ARRAY (적외선검출기 READOUT CONTROLLER 개발)

  • Cho, Seoung-Hyun;Jin, Ho;Nam, Uk-Won;Cha, Sang-Mok;Lee, Sung-Ho;Yuk, In-Soo;Park, Young-Sik;Pak, Soo-Jong;Han, Won-Yong;Kim, Sung-Soo
    • Publications of The Korean Astronomical Society
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    • v.21 no.2
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    • pp.67-74
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    • 2006
  • We have developed a control electronics system for an infrared detector array of KASINICS (KASI Near Infrared Camera System), which is a new ground-based instrument of the Korea Astronomy and Space science Institute (KASI). Equipped with a $512{\times}512$ InSb array (ALADDIN III Quadrant, manufactured by Raytheon) sensitive from 1 to $5{\mu}m$, KASINICS will be used at J, H, Ks, and L-bands. The controller consists of DSP(Digital Signal Processor), Bias, Clock, and Video boards which are installed on a single VME-bus backplane. TMS320C6713DSP, FPGA(Field Programmable Gate Array), and 384-MB SDRAM(Synchronous Dynamic Random Access Memory) are included in the DSP board. DSP board manages entire electronics system, generates digital clock patterns and communicates with a PC using USB 2.0 interface. The clock patterns are downloaded from a PC and stored on the FPGA. UART is used for the communication with peripherals. Video board has 4 channel ADC which converts video signal into 16-bit digital numbers. Two video boards are installed on the controller for ALADDIN array. The Bias board provides 16 dc bias voltages and the Clock board has 15 clock channels. We have also coded a DSP firmware and a test version of control software in C-language. The controller is flexible enough to operate a wide range of IR array and CCD. Operational tests of the controller have been successfully finished using a test ROIC (Read-Out Integrated Circuit).

An Efficient Page-Level Mapping Algorithm for Handling Write Requests in the Flash Translation Layer by Exploiting Temporal Locality (플래시 변환 계층에서 시간적 지역성을 이용하여 쓰기 요청을 처리하는 효율적인 페이지 레벨 매핑 알고리듬)

  • Li, Hai-Long;Hwang, Sun-Young
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.41 no.10
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    • pp.1167-1175
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    • 2016
  • This paper proposes an efficient page-level mapping algorithm that reduces the erase count in the FTL for flash memory systems. By maintaining the weight for each write request in the request buffer, the proposed algorithm estimates the degree of temporal locality for each incoming write request. To exploit temporal locality deliberately for determination of hot request, the degree of temporal locality should be much higher than the reference point determined experimentally. While previous LRU algorithm treats a new write request to have high temporal locality, the proposed algorithm allows write requests that are estimated to have high temporal locality to access hot blocks to store hot data intensively. The pages are more frequently updated in hot blocks than warm blocks. A hot block that has most of invalid pages is always selected as victim block at Garbage Collection, which results in delayed erase operation and in reduced erase count. Experimental results show that erase count is reduced by 9.3% for real I/O workloads, when compared to the previous LRU algorithm.

AS B-tree: A study on the enhancement of the insertion performance of B-tree on SSD (AS B-트리: SSD를 사용한 B-트리에서 삽입 성능 향상에 관한 연구)

  • Kim, Sung-Ho;Roh, Hong-Chan;Lee, Dae-Wook;Park, Sang-Hyun
    • The KIPS Transactions:PartD
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    • v.18D no.3
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    • pp.157-168
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    • 2011
  • Recently flash memory has been being utilized as a main storage device in mobile devices, and flashSSDs are getting popularity as a major storage device in laptop and desktop computers, and even in enterprise-level server machines. Unlike HDDs, on flash memory, the overwrite operation is not able to be performed unless it is preceded by the erase operation to the same block. To address this, FTL(Flash memory Translation Layer) is employed on flash memory. Even though the modified data block is overwritten to the same logical address, FTL writes the updated data block to the different physical address from the previous one, mapping the logical address to the new physical address. This enables flash memory to avoid the high block-erase cost. A flashSSD has an array of NAND flash memory packages so it can access one or more flash memory packages in parallel at once. To take advantage of the internal parallelism of flashSSDs, it is beneficial for DBMSs to request I/O operations on sequential logical addresses. However, the B-tree structure, which is a representative index scheme of current relational DBMSs, produces excessive I/O operations in random order when its node structures are updated. Therefore, the original b-tree is not favorable to SSD. In this paper, we propose AS(Always Sequential) B-tree that writes the updated node contiguously to the previously written node in the logical address for every update operation. In the experiments, AS B-tree enhanced 21% of B-tree's insertion performance.

A Prefetching and Memory Management Policy for Personal Solid State Drives (개인용 SSD를 위한 선반입 및 메모리 관리 정책)

  • Baek, Sung-Hoon
    • The KIPS Transactions:PartA
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    • v.19A no.1
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    • pp.35-44
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    • 2012
  • Traditional technologies that are used to improve the performance of hard disk drives show many negative cases if they are applied to solid state drives (SSD). Access time and block sequence in hard disk drives that consist of mechanical components are very important performance factors. Meanwhile, SSD provides superior random read performance that is not affected by block address sequence due to the characteristics of flash memory. Practically, it is recommended to disable prefetching if a SSD is installed in a personal computer. However, this paper presents a combinational method of a prefetching scheme and a memory management that consider the internal structure of SSD and the characteristics of NAND flash memory. It is important that SSD must concurrently operate multiple flash memory chips. The I/O unit size of NAND flash memory tends to increase and it exceeded the block size of operating systems. Hence, the proposed prefetching scheme performs in an operating unit of SSD. To complement a weak point of the prefetching scheme, the proposed memory management scheme adaptively evicts uselessly prefetched data to maximize the sum of cache hit rate and prefetch hit rate. We implemented the proposed schemes as a Linux kernel module and evaluated them using a commercial SSD. The schemes improved the I/O performance up to 26% in a given experiment.

Failure Analysis of Ferroelectric $(Bi,La)_4Ti_3O_{12}$ Capacitor in Fabricating High Density FeRAM Device (고밀도 강유전체 메모리 소자 제작 시 발생하는 $(Bi,La)_4Ti_3O_{12}$ 커패시터의 불량 분석)

  • Kim, Young-Min;Jang, Gun-Eik;Kim, Nam-Kyeong;Yeom, Seung-Jin;Hong, Suk-Kyoung;Kweon, Soon-Yong
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2007.06a
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    • pp.257-257
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    • 2007
  • 고밀도 FeRAM (Ferroe!ectric Random Access Memory) 소자를 개발하기 위해서는 강유전체 물질을 이용한 안정적인 스텍형의 커패시터 개발이 필수적이다. 특히 $(Bi,La)_4Ti_3O_{12}$ (BLT) 강유전체 물질을 이용하는 경우에는 낮은 열처리 온도에서도 균질하고 높은 값의 잔류 분극 값을 확보하는 것이 가장 중요한 과제 중의 하나이다. 불행히도, BLT 물질은 a-축으로는 약 $50\;{\mu}C/cm^2$ 정도의 높은 잔류 분극 값을 갖지만, c-축 방향으로는 $4\;{\mu}C/cm^2$ 정도의 낮은 잔류 분극 값을 나타내는 동의 강한 비등방성 특성을 보인다. 따라서 BLT 박막에서 각각 입자들의 크기 및 결정 방향성을 세밀하게 제어하는 것은 무엇보다 중요하다. 본 연구에서는 16 Mb의 1T/1C (1-transistor/1-capacitor) 형의 FeRAM 소자를 BLT 박막을 적용하여 제작하였다. 솔-젤 (sol-gel) 용액을 이용하여 스핀코팅법으로 BLT 박막을 증착하고, 후속 열처리 공정을 RTP (rapid thermal process) 공정을 이용하여 수행하였다. 커패시터의 하부 전극 및 상부 전극은 각각 Pt/IrOx/lr 및 Pt을 적용하였다. 반응성 이온 에칭 (RIE: reactive ion etching) 공정을 이용하여 커패시터를 형성시킨 후, 32k-array (unit capacitor: $0.68\;{\mu}m$) 패턴에서 측정한 스위칭 분극 (dP=P*-P^) 값은 약 $16\;{\mu}C/cm^2$ 정도이고, 웨이퍼 내에서의 균일도도 2.8% 정도로 매우 우수한 특성을 보였다. 그러나 단위 셀들의 특성을 평가하기 위하여 bit-line의 전압을 측정한 결과, 약 10% 정도의 커패시터에서 불량이 발생하였다. 그리고 이러한 불량 젤들은 매우 불규칙적으로 분포함을 확인할 수 있었다. 이러한 불량 원인을 파악하기 위하여 양호한 젤과 불량이 발생한 셀에서의 BLT 박막의 미세구조를 분석하였다. 양호한 셀의 BLT 박막 입자들은 불량한 셀에 비하여 작고 비교적 균일한 크기를 갖고 있었다. 이에 비하여 불량한 셀에서의 BLT 박막에는 과대 성장한 입자들이 존재하고 이에 따라서 입자 크기가 매우 불균질한 것으로 확인되었다. 또 이러한 과대 성장한 입자들은 거의 모두 c-축 배향성을 나타내었다. 이상의 실험 결과들로부터, BLT 박막을 이용하여 제작한 FeRAM 소자에서 발생하는 불규칙한 셀 불량의 주된 원인은 c-축 배향성을 갖는 과대 성장한 입자의 생성임을 알 수 있었다. 즉 BLT 박막을 이용하여 FeRAM 소자를 제작하는 경우, 균일한 크기의 입자 및 c-축 배향성의 입자 억제가 매우 중요한 기술적 요소임을 알 수 있었다.

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Magnetization Switching of MTJs with CoFeSiB/Ru/CoFeSiB Free Layers (CoFeSiB/Ru/CoFeSiB 자유층을 갖는 자기터널 접합의 스위칭 자기장)

  • Lee, S.Y.;Lee, S.W.;Rhee, J.R.
    • Journal of the Korean Magnetics Society
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    • v.17 no.3
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    • pp.124-127
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    • 2007
  • Magnetic tunnel junctions (MTJs), which consisted of amorphous CoFeSiB layers, were investigated. The CoFeSiB layers were used to substitute for the traditionally used CoFe and/or NiFe layers with an emphasis given on understanding the effect of the amorphous free layer on the switching characteristics of the MTJs. CoFeSiB has a lower saturation magnetization ($M_s\;:\;560\;emu/cm^3$) and a higher anisotropy constant ($K_u\;:\;2800\;erg/cm^3$) than CoFe and NiFe, respectively. An exchange coupling energy ($J_{ex}$) of $-0.003\;erg/cm^2$ was observed by inserting a 1.0 nm Ru layer in between CoFeSiB layers. In the Si/$SiO_2$/Ta 45/Ru 9.5/IrMn 10/CoFe 7/$AlO_x$/CoFeSiB 7 or CoFeSiB (t)/Ru 1.0/CoFeSiB (7-t)/Ru 60 (in nm) MTJs structure, it was found that the size dependence of the switching field originated in the lower $J_{ex}$ using the experimental and simulation results. The CoFeSiB synthetic antiferromagnet structures were proved to be beneficial for the switching characteristics such as reducing the coercivity ($H_c$) and increasing the sensitivity in micrometer size, even in submicrometer sized elements.

Change of NDVI by Surface Reflectance Based on KOMPSAT-3/3A Images at a Zone Around the Fukushima Daiichi Nuclear Power Plant (후쿠시마 제1 원전 주변 지역의 KOMPSAT-3/3A 영상 기반 지표반사도 적용 식생지수 변화)

  • Lee, Jihyun;Lee, Juseon;Kim, Kwangseob;Lee, Kiwon
    • Korean Journal of Remote Sensing
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    • v.37 no.6_3
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    • pp.2027-2034
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    • 2021
  • Using multi-temporal KOMPSAT-3/3A high-resolution satellite images, the Normalized Difference Vegetation Index (NDVI) for the area around the Fukushima daiichi nuclear power plant was determined, and the pattern of vegetation changes was analyzed. To calculate the NDVI, surface reflectance from the KOMPSAT-3/3A satellite image was used. Satellite images from four years were used, and the zones where the images overlap was designated as the area of interest (AOI) for the study, and by setting a profile passing through highly vegetated area as a data analysis method, the changes by year were examined. In addition, random points were extracted within the AOI and displayed as a box plot to quantitatively indicate change of NDVI distribution pattern. The main results of this study showed that the NDVI in 2014 was low within AOI in the vicinity of the nuclear power plant, but vegetated area continued to expand until 2021. These results were also confirmed in the change monitoring results shown in a profile or box plot. In disaster areas where access is restricted, such as the Fukushima nuclear power plant area, where it is difficult to collect field data, obtaining land cover classification products with high accuracy using satellite images is challenging, so it is appropriate to analyze them using primary outputs such as vegetation indices obtained from high-resolution satellite imagery. It is necessary to establish an international cooperation system for jointly utilizing satellite images. Meanwhile, to periodically monitor environmental changes in neighboring countries that may affect the Korean peninsula, it is necessary to establish utilization models and systems using high-resolution satellite images.