• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.2A
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• pp.143-151
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• 2007

One of the consideration things to design protocol in wireless sensor networks is to maximize lifetime of sensor node as reducing energy consumption. In this paper propose reserve based multichannel CSMA mac protocol for minimizing energy consumption which arise from collision and waiting retransmission at channel access process in mac layer Each sensor node which constitute sensor networks has data channel and control channel. And as sensor node reserve channel for data transmission by using control channel and receipt node allow reservation node to use data channel, sending node can abbreviate try of retransmission after random interval time. Also, When sending node delivers selects option channel in available channels to receipt node, the receipt node decide whether the channel is available to oneself and through the result select transmission channel ultimately. Performance evaluation compare with previous simple multichannel CSMA.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.8
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• pp.9-15
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• 2010

This paper presents an analysis of asynchronous multicarrier-code division multiple access (MC-CDMA) uplink systems over frequency-selective multipath fading channels when the frequency offsets (FOs) of all users are random variables and the frequency offset for the desired user is compensated. The effect of a residual frequency offset(RFO) on the average bit error rate (BER) is evaluated by the semi-analytical method, then the approximated BER performance is obtained as a closed-form expression. Moreover, the signal to noise ratio (SNR) loss caused by RFO is evaluated. Derived results show that the performance degradation due to RFO is negligible if the estimation error of RFO for the desired user is less than the normalized value of 0.1.

• Journal of KIISE:Information Networking
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• v.30 no.1
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• pp.9-16
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• 2003

In this paper, we propose a method for supporting VCR operations in a patching based multicast VOD system. Random access, pause and resume operations are supported in our system, and the channel and session scheduling algorithms for the VCR operations are proposed. When it is necessary to join a sharable multicast channel in the admission control for the VCR operations, the patching technique, which shares an on-going regular channel and allocates a new patching channel for the missing data, is used. Therefore, unlike the previous approach that allocates an excessive number of I-channels, service latency is minimized and channel usage is optimized in our system. Moreover buffered data. which is saved in disk during patching, is reused to prevent unnecessary patching channel allocation. For this. the patching management information is extended and a buffed data management scheme is proposed. In our system, the First-Come-First-Served scheduling is used to inform clients the service latency for the VCR operations immediately.

• Publications of The Korean Astronomical Society
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• v.21 no.2
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• pp.67-74
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• 2006

We have developed a control electronics system for an infrared detector array of KASINICS (KASI Near Infrared Camera System), which is a new ground-based instrument of the Korea Astronomy and Space science Institute (KASI). Equipped with a $512{\times}512$ InSb array (ALADDIN III Quadrant, manufactured by Raytheon) sensitive from 1 to $5{\mu}m$, KASINICS will be used at J, H, Ks, and L-bands. The controller consists of DSP(Digital Signal Processor), Bias, Clock, and Video boards which are installed on a single VME-bus backplane. TMS320C6713DSP, FPGA(Field Programmable Gate Array), and 384-MB SDRAM(Synchronous Dynamic Random Access Memory) are included in the DSP board. DSP board manages entire electronics system, generates digital clock patterns and communicates with a PC using USB 2.0 interface. The clock patterns are downloaded from a PC and stored on the FPGA. UART is used for the communication with peripherals. Video board has 4 channel ADC which converts video signal into 16-bit digital numbers. Two video boards are installed on the controller for ALADDIN array. The Bias board provides 16 dc bias voltages and the Clock board has 15 clock channels. We have also coded a DSP firmware and a test version of control software in C-language. The controller is flexible enough to operate a wide range of IR array and CCD. Operational tests of the controller have been successfully finished using a test ROIC (Read-Out Integrated Circuit).