• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.II
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• pp.1183-1186
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• 2005

A new reset method for high contrast ratio and reduction of the reset time is presented. In this new reset method, except the first subfield, a new reset pulse with only ramp-up period is adopted. In this reset method, from the third subfield, the background luminance generated during the reset period is theoretically zero until the first subfield of the following frame. Employing the new reset method, the dark room contrast ratio improved to 3084.7:1 from 189.1:1 of the conventional reset method. The new reset method reduced the required time for reset per subfield to 160us except the first subfield.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2003년도 International Meeting on Information Display
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• pp.756-759
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• 2003

We measure the spatiotemporal wall charge distributions on sustain and address electrodes during reset period in an ac PDP cell using the longitudinal electro-optic amplitude modulation method. We apply several reset waveforms like as ramp, exponentially growing and high voltage pulse, and compare the wall charge characteristics on address electrode as well as sustain electrodes for each reset waveforms.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2002년도 International Meeting on Information Display
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• pp.57-60
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• 2002

This paper deals with the effect of ramp-type erase pulse waveform on the high temperature driving characteristics of ac PDP driven by ramp up-down reset waveform. The experimental results show that the discharge characteristics in the reset period are significantly affected by the erase pulse waveform and ambient temperature. The firing voltage is increased with ambient temperature. This can cause misfirings during the sustain period and should be avoided. As one of possible solutions, we propose the optimization of erasing pulse shape.

• Journal of Information Display
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• 제7권1호
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• pp.25-29
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• 2006

By the voltage threshold (Vt) close-curve measurement method, the changes in the discharge characteristics such as a firing voltage and IR emission among the three electrodes were examined relative to the low or high panel temperature ranging from -10 to $80^{\circ}$. The variation in the panel temperature was found significantly influence the surface discharge between the MgO surfaces rather than the plate gap discharge between the MgO and phosphor layers. Based on this experimental observation, a modified reset waveform that alleviates the surface discharge during a ramp-up and -down period was deeloped. By adopting the proposed reset waveform, a stable address discharge could be obtained irrespective of the panel temperature variation.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제51권11호
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• pp.536-540
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• 2002

This paper proposes a method to drive an AC plasma display panel(PDP) with a significantly improved contrast ratio. In the proposed method, during the first sub-field of one frame, all PDP cells are reset by the ramp waveform, and during the other sub-field, only the cells turned on in the previous sub-field are reset. No light is emitted during the reset period of every sub-field except the first sub-field. For a 10-bit picture, the luminance of the dark level for the proposed method is 10 times lower than that for the conventional method, in which the ramp waveform for the reset is used in every sub-field. Accordingly, the contrast ratio for the proposed method is 10 times higher than that for the conventional method. For the 10-bit picture, the measured contrast ratio was about 3080:1 for the proposed method and about 285:1 with the conventional method, a result the contrast ratio has been increased in 10.8 times. This result shows that the proposed method can realize an image with high contrast ratio.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 제37회 하계학술대회 논문집 C
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• pp.1544-1545
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• 2006

In this paper, we present a new reset waveform for a large-sustain-gap structure in at PDPs. In the driving of the large-sustain-gap structure with a conventional ramp reset waveform, we cannot avoid the condition of an address being a cathode, which causes lots of trouble in stabilizing a reset discharge. To solve these problems, we use the square pulse instead of the conventional rising ramp pulse. Before making a strong discharge between the address (cathode) and scan (anode) electrodes, we make a priming discharge between the address (anode) and the scan (cathode) electrodes to stabilize the strong discharge in which the address electrodes are the cathode. With this scheme, we obtained 60V minimum address voltage and 145V maximum address voltage in $250{\mu}m$ and $350{\mu}m$ gap structures.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2000년도 제18회 학술발표회 논문개요집
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• pp.197-197
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• 2000

AC-PDP의 구동 요소 중 중요한 것은 벽전하와 그로부터 유도되는 벽전압, 그리고 프라이밍입자(priming partical)의 밀도 변화라고 할 수 있다. 패널의 초기화가 전구간의 방전을 좌우하기 때문에 초기화 펄스의 기울기에 따른 방전현상을 이해하고자 각 구간에서의 전기-광학적 특성과 함께 휘도와 효율의 관점에서 연구 조사하였다. 본 실험에서 사용한 reset 펄스파형은 셀의 방전개시전압과 인가전압사이의 차이가 적고, 초기 프라이밍 입자와 단위시간당 전자에 공급되는 에너지가 적은 램프형태의 초기화 펄스를 사용하였다. 실험장치는 VDS(versatile driving simulator)시스템을 이용하였다. 실험결과 reset의 기울기가 커질수록 반응시간이 빨라지며, 약방전의 형태를 고속이미지로 확인하였다.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.I
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• pp.631-634
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• 2005

We propose a new address-while-display (AWD) driving method to obtain a high contrast ratio and a wide driving margin which is composed of a short ramp reset period, a sustain period and an address period as the basic unit. The short ramp reset (SRR) pulse made it possible to assure the wide operating voltage margin and minimize the background luminance by redistributing the wall charges between address and scan electrode. As a result, a high dark room contrast ratio of 10000 to 1 could be obtained with a wide operating voltage margin of 40V for stable address.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2008년도 International Meeting on Information Display
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• pp.388-391
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• 2008

A new reset waveform with negative ramp pulse was proposed. Comparative experiments between the negative and positive waveforms were performed. During reset period, IR distributions and luminance of black and white conditions were measured with the 42-inch XGA PDP module. The negative waveform improved contrast ratio about 15.4 ~ 22.5 % than the positive waveform by lowing the black luminance in reset period. Z bias (= Vbb) of the positive waveform was 27 V higher than the negative waveform.

• Journal of Power Electronics
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• 제7권4호
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• pp.278-285
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• 2007

Recently, plasma display panels (PDP) have become the most promising candidate in the market for large screen size flat panel displays. PDPs have many merits such as a fast display response time and wide viewing angle. However, there are still concerns about high cost because they require complex driving circuits composed of high power switching devices to generate various voltage waveforms for three operational modes of reset, scan, and sustain. Conventional PDP driving circuits use path switches for voltage separation and a scan switch to offer a scan voltage for reset and scan operations, respectively. In addition, there exist reset switches to initialize PDPs by regulating the wall charge conditions with ramp shaped pulses, which means the necessity of specific power devices for the reset operation. Because power for the plasma discharge accompanied by a large current is transferred to a panel via path switches, high power rating switches are used for path switches. Therefore, this paper proposes a novel low-cost PDP driving scheme achieved by not only eliminating path switches but also merging the function of reset switches into other switches used for sustain or scan operations. The simulated voltage waveforms of the proposed topology and experimental results implemented in a 42-inch panel to demonstrate the validity of using a new gate driver that merges the functions of power switches are presented.