• Title/Summary/Keyword: quasi-floating gate

Search Result 2, Processing Time 0.016 seconds

Simulation Study on a Quasi Fermi Energy Movement in the Floating Body Region of FITET (Field-induced Inter-band Tunneling Effect Transistor)

  • Song, Seung-Hwan;Kim, Kyung-Rok;Kang, Sang-Woo;Kim, Jin-Ho;Kang, Kwon-Chil;Shin, Hyung-Cheol;Lee, Jong-Duk;Park, Byung-Gook
    • Proceedings of the IEEK Conference
    • /
    • 2005.11a
    • /
    • pp.679-682
    • /
    • 2005
  • Negative-differential conductance (NDC) characteristics as well as negative-differential trans-conductance (NDT) characteristics have been observed in the room temperature I-V characteristics of Field-induced Inter-band Tunneling Effect Transistors (FITETs). These characteristics have been explained with inter-band tunneling physics, from which, inter-band tunneling current flows when the energy bands of degenerately doped regions align, and it does not flow when they don't. FITET is an SOI device and the body region is not directly connected to the external terminal. Therefore, Fermi energy in the body region is determined by electrical coupling among four regions - gate, source, drain and substrate. So, a quasi Fermi energy of the majority carriers in the floating body region can be changed by external voltages, and this causes the energy band movements in the body region, which determine whether the energy bands between degenerately doped junctions aligns or not. This is a key point for an explanation of NDT and NDC characteristics. In this paper, a quasi Fermi energy movement in the floating body region of FITET was investigated by a device simulation. This result was applied for the description of relation between quasi Fermi energy in the body region and external gate bias voltage.

  • PDF

Design of Two-Stage Class AB CMOS Buffers: A Systematic Approach

  • Martin, Antonio Lopez;Miguel, Jose Maria Algueta;Acosta, Lucia;Ramirez-Angulo, Jaime;Carvajal, Ramon Gonzalez
    • ETRI Journal
    • /
    • v.33 no.3
    • /
    • pp.393-400
    • /
    • 2011
  • A systematic approach for the design of two-stage class AB CMOS unity-gain buffers is proposed. It is based on the inclusion of a class AB operation to class A Miller amplifier topologies in unity-gain negative feedback by a simple technique that does not modify quiescent currents, supply requirements, noise performance, or static power. Three design examples are fabricated in a 0.5 ${\mu}m$ CMOS process. Measurement results show slew rate improvement factors of approximately 100 for the class AB buffers versus their class A counterparts for the same quiescent power consumption (< 200 ${\mu}W$).