• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2005년도 ICCAS
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• pp.868-871
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• 2005

In this article, presents an analog multiplier using a general-purpose operational amplifier (opamp). The realization method is based on the quarter-square technique, which utilize the square-law characteristic of the class AB output stage of the opamp. The experimental results verifying the proposed multiplier performances are also included. The linearity error and the total harmonic distortion is about 0.8% and 1.6%, respectively.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2000년도 제15차 학술회의논문집
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• pp.318-318
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• 2000

Current signal square based on switch current is presented in this article. This is the new technique that can design current signal square circuit by using switch-current memory cell, current square and sample and hold technique, which have been presented by the general switch-current. This principle which is present have the good electrical characteristics such as the low input impedance, high output impedance and high frequency response. The system can also operate in the audio frequency range to the high frequency current signal. The system application of this technique can be apply to the current signal multiplier by quarter square technique. The experimental results agree well with the theory as high accuracy and linearity.

• 대한전자공학회논문지SD
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• 제39권6호
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• pp.26-33
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• 2002

본 논문에서는 포화영역에서 동작하는 MOS트랜지스터의 제곱특성과 소오스를 결합한 차동회로의 뺄셈기능을 이용하여 구현한 quarter-square기술방식의 새로운 4상한 MOS아날로그 곱셈기를 제안하였다. 본 논문에서 제안된 회로는 p-well CMOS 공정으로 설계-제작되어 특성측정을 하였다. 제작된 곱셈회로의 입력에 공급전압의 50%의 크기를 기치는 신호를 인가하였을 때, 1%미만의 왜율을 갖는 -1.3V에서 1.3V크기의 출력신호를 얻었고, 0에서30㎒까지의 -3㏈ 주파수대역을 측정하였고, 81㏈의 출력유동범위와 40㎽의 전력을 소모하였으며, 0.54㎟의 칩면적을 차지하였다. 제안된 곱셈회로는 회로구성이 간단할 뿐만 아니라, 입력신호가 한 개의 트랜지스터를 통하여 출력에 전달되므로 고주파 응용에도 적합하다.

• Journal of electromagnetic engineering and science
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• 제18권2호
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• pp.117-128
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• 2018

In this paper, compact linear dual polarized series-fed $1{\times}2$ linear and $2{\times}2$ planar arrays antennas for airborne SAR applications are proposed. The proposed antenna design consists of a square radiating patch that is placed on top of the substrate, a quarter wave transformer and $50-{\Omega}$ matched transformer. Matching between a radiating patch and the $50-{\Omega}$ microstrip line is accomplished through a direct coupled-feed technique with the help of an impedance inverter (${\lambda}/4$ impedance transformer) placed at both horizontal and vertical planes, in the case of the $2{\times}2$ planar array. The overall size for the prototype-1 and prototype-2 fabricated antennas are $1.9305{\times}0.9652{\times}0.05106{{\lambda}_0}^3$ and $1.9305{\times}1.9305{\times}0.05106{{\lambda}_0}^3$, respectively. The fabricated structure has been tested, and the experimental results are similar to the simulated ones. The CST MWS simulated and vector network analyzer measured reflection coefficient ($S_{11}$) results were compared, and they indicate that the proposed antenna prototype-1 yields the impedance bandwidth >140 MHz (9.56-9.72 GHz) defined by $S_{11}$<-10 dB with 1.43%, and $S_{21}$<-25 dB in the case of prototype-2 (9.58-9.74 GHz, $S_{11}$< -10 dB) >140 MHz for all the individual ports. The surface currents and the E- and H-field distributions were studied for a better understanding of the polarization mechanism. The measured results of the proposed dual polarized antenna were in accordance with the simulated analysis and showed good performance of the S-parameters and radiation patterns (co-pol and cross-pol), gain, efficiency, front-to-back ratio, half-power beam width) at the resonant frequency. With these features and its compact size, the proposed antenna will be suitable for X-band airborne synthetic aperture radar applications.