• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.868-871
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• 2005

In this article, presents an analog multiplier using a general-purpose operational amplifier (opamp). The realization method is based on the quarter-square technique, which utilize the square-law characteristic of the class AB output stage of the opamp. The experimental results verifying the proposed multiplier performances are also included. The linearity error and the total harmonic distortion is about 0.8% and 1.6%, respectively.

• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.318-318
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• 2000

Current signal square based on switch current is presented in this article. This is the new technique that can design current signal square circuit by using switch-current memory cell, current square and sample and hold technique, which have been presented by the general switch-current. This principle which is present have the good electrical characteristics such as the low input impedance, high output impedance and high frequency response. The system can also operate in the audio frequency range to the high frequency current signal. The system application of this technique can be apply to the current signal multiplier by quarter square technique. The experimental results agree well with the theory as high accuracy and linearity.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.6
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• pp.26-33
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• 2002

In this paper, a new four-quadrant MOS analog multiplier Is proposed using the quarter-square technique, which is based on the quadratic characteristics of MOS transistor operating in the saturation region and the difference operation of a source-coupled differential circuits. The proposed circuit has been fabricated in a p-well CMOS process. The multiplier achieves a total harmonic distortion of less than 1 percent for the both input ranges of 50 percent of power supply, a -3㏈ bandwidth of 30㎒ a dynamic range of 81㏈ and a power consumption of 40㎽. The active chip area is 0.54㎟. The supposed multiplier circuit is simple and adjust high frequency application because one input signal transfer output by one transistor.

• Journal of electromagnetic engineering and science
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• v.18 no.2
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• pp.117-128
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• 2018

In this paper, compact linear dual polarized series-fed $1{\times}2$ linear and $2{\times}2$ planar arrays antennas for airborne SAR applications are proposed. The proposed antenna design consists of a square radiating patch that is placed on top of the substrate, a quarter wave transformer and $50-{\Omega}$ matched transformer. Matching between a radiating patch and the $50-{\Omega}$ microstrip line is accomplished through a direct coupled-feed technique with the help of an impedance inverter (${\lambda}/4$ impedance transformer) placed at both horizontal and vertical planes, in the case of the $2{\times}2$ planar array. The overall size for the prototype-1 and prototype-2 fabricated antennas are $1.9305{\times}0.9652{\times}0.05106{{\lambda}_0}^3$ and $1.9305{\times}1.9305{\times}0.05106{{\lambda}_0}^3$, respectively. The fabricated structure has been tested, and the experimental results are similar to the simulated ones. The CST MWS simulated and vector network analyzer measured reflection coefficient ($S_{11}$) results were compared, and they indicate that the proposed antenna prototype-1 yields the impedance bandwidth >140 MHz (9.56-9.72 GHz) defined by $S_{11}$<-10 dB with 1.43%, and $S_{21}$<-25 dB in the case of prototype-2 (9.58-9.74 GHz, $S_{11}$< -10 dB) >140 MHz for all the individual ports. The surface currents and the E- and H-field distributions were studied for a better understanding of the polarization mechanism. The measured results of the proposed dual polarized antenna were in accordance with the simulated analysis and showed good performance of the S-parameters and radiation patterns (co-pol and cross-pol), gain, efficiency, front-to-back ratio, half-power beam width) at the resonant frequency. With these features and its compact size, the proposed antenna will be suitable for X-band airborne synthetic aperture radar applications.