• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2009년도 추계학술대회 초록집
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• pp.155-155
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• 2009

The copper plating was deposited by pulse reverse current (PRC) method with additives. The all specimens were first immersted in 10% H2SO4 for 10 minutes, and then were rinsed with deionized water. The current densities of forward pulse were 400mA/$cm^2$, and those of reverse pulse were 1900mA/$cm^2$ and 100mA/$cm^2$. Results are compared for different additives for pulse plating conditions. When it added in Only CH4N2S (TU) or only C10H13NO3S (SVH), the effect of surface side growth of Cu was not different. But when it added in TU and SVH, surface side growth of Cu decreased. Polarization curves were measured from OCP to -0.7 V at a rate of 1mV/sec. Each specimen was observed under the PHENOM to see surface morphology.

• 한국재료학회지
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• 제19권3호
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• pp.151-155
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• 2009

Micro-scale copper bumps for build-up PCB were electroplated using a pulse-reverse method. The effects of the current density, pulse-reverse ratio and brightener concentration of the electroplating process were investigated and optimized for suitable performance. The electroplated micro-bumps were characterized using various analytical tools, including an optical microscope, a scanning electron microscope and an atomic force microscope. Surface analysis results showed that the electroplating uniformity was viable in a current density range of 1.4-3.0 A/$dm^2$ at a pulse-reverse ratio of 1. To investigate the brightener concentration on the electroplating properties, the current density value was fixed at 3.0 A/$dm^2$ as a dense microstructure was achieved at this current density. The brightener concentration was varied from 0.05 to 0.3 ml/L to study the effect of the concentration. The optimum concentration for micro-bump electroplating was found to be 0.05 ml/L based on the examination of the electroplating properties of the bump shape, roughness and grain size.

• 마이크로전자및패키징학회지
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• 제14권3호
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• pp.51-55
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• 2007

Ni-Fe 전해도금 시 전류밀도, 펄스주기와 전류인가 방식, 도금욕의 Fe 이온의 농도, 첨가제 등의 인자들이 도금 층의 조성, 표면형상, 표면 경도에 미치는 영향에 관하여 연구하였다. 시편에 가해지는 전류밀도, 전류인가방식과 Fe이온의 농도를 변화시킴으로써 Ni-Fe의 도금 층 내에 Ni-Fe의 조성을 조절하는 것이 가능하였고 또한 첨가제의 양을 변화시킴으로써 표면형상이 변화됨을 확인하였다. PC를 사용한 경우 직류를 사용한 경우보다 높은 $550{\sim}600Hv$의 경도값을 얻을 수 있었다. 사카린을 첨가한 경우 도금층의 잔류응력을 낮추어 균열이 없는 도금층을 얻었다. Ni-Fe의 단면의 조성을 분석함으로써 도금 층의 두께에 따른 조성의 변화를 확인하였다.

• 마이크로전자및패키징학회지
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• 제12권2호
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• pp.129-134
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• 2005

SiP의 3D패키지에 있어서 구리도금은 매우 중요한 역할을 한다 이러한 구리 도금의 조건을 알아보기 위하여 조건이 다른 전해질에서 전기화학적 I-V특성을 분석하였다. 첨가제로 억제제와 촉진제의 특성을 분석하였다. 3D 패키지에 있어서 직경 50, 75, $100{\mu}m$의 via를 사용하였다. Via의 높이는 $100{\mu}m$로 동일하였다. Via의 내부는 확산방지층으로 Ta을 전도성 씨앗층으로 Cu를 magnetron 스퍼터링 방법으로 도포하였다. 직류, 펄스, 펄스-역펄스 등 전류의 파형을 변화시키면서 구리 도금을 하였다. 직류만 사용하였을 경우에는 결함 없이 via가 채워지지 않았으며 펄스도금을 한 경우 구리 충진이 개선을 되었으나 결함이 발생하였다. 펄스-역펄스를 사용한 경우 결함 없는 구리 충진층을 얻을 수 있었다.

• 대한금속재료학회지
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• 제49권5호
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• pp.388-394
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• 2011

High speed copper filling into TSV (through-silicon-via) for three dimensional stacking of Si chips was investigated. For this study, a tapered via was prepared on a Si wafer by the DRIE (deep reactive ion etching) process. The via had a diameter of 37${\mu}m$ at the via opening, and 32${\mu}m$ at the via bottom, respectively and a depth of 70${\mu}m$. $SiO_2$, Ti, and Au layers were coated as functional layers on the via wall. In order to increase the filling ratio of Cu into the via, a PPR (periodic pulse reverse) wave current was applied to the Si chip during electroplating, and a PR (pulse reverse) wave current was applied for comparison. After Cu filling, the cross sections of the vias was observed by FE-SEM (field emission scanning electron microscopy). The experimental results show that the tapered via was filled to 100% at -5.85 mA/$cm^2$ for 60 min of plating by PPR wave current. The filling ratio into the tapered via by the PPR current was 2.5 times higher than that of a straight via by PR current. The tapered via by the PPR electroplating process was confirmed to be effective to fill the TSV in a short time.

• Journal of Welding and Joining
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• 제32권3호
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• pp.11-18
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• 2014

TSV(through silicon via) filling technology is making a hole in Si wafer and electrically connecting technique between front and back of Si die by filling with conductive metal. This technology allows that a three-dimensionally connected Si die can make without a large number of wire-bonding. These TSV technologies require various engineering skills such as forming a via hole, forming a functional thin film, filling a conductive metal, polishing a wafer, chip stacking and TSV reliability analysis. This paper addresses the TSV filling using Cu electrodeposition. The impact of plating conditions with additives and current density on electrodeposition will be considered. There are additives such as accelerator, inhibitor, leveler, etc. suitably controlling the amount of the additive is important. Also, in order to fill conductive material in whole TSV hole, current wave forms such as PR(pulse reverse), PPR(periodic pulse reverse) are used. This study about semiconductor packaging will be able to contribute to the commercialization of 3D TSV technology.

• 한국재료학회지
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• 제18권3호
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• pp.117-122
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• 2008

Micro-sized bumps on a multi-layered build-up PCB were fabricated by pulse-reverse copper electroplating. The values of the current density and brightener content for the electroplating were optimized for suitable performance with maximum efficiency. The micro-bumps thus electroplated were characterized using a range of analytical tools that included an optical microscope, a scanning electron microscope, an atomic force microscope and a hydraulic bulge tester. The optical microscope and scanning electron microscope analyses results showed that the uniformity of the electroplating was viable in the current density range of $2-4\;A/dm^2$; however, the uniformity was slightly degraded as the current density increased. To study the effect of the brightener concentration, the concentration was varied from zero to 1.2 ml/L. The optimum concentration for micro-bump electroplating was found to be 0.6 ml/L based on an examination of the electroplating properties, including the roughness, yield strength and grain size.

• 대한금속재료학회지
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• 제48권7호
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• pp.667-673
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• 2010

Copper filling into TSV (through-silicon-via) and reduction of the filling time for the three dimensional chip stacking were investigated in this study. A Si wafer with straight vias - $30\;{\mu}m$ in diameter and $60\;{\mu}m$ in depth with $200\;{\mu}m$ pitch - where the vias were drilled by DRIE (Deep Reactive Ion Etching) process, was prepared as a substrate. $SiO_2$, Ti and Au layers were coated as functional layers on the via wall. In order to reduce the time required complete the Cu filling into the TSV, the PPR (periodic pulse reverse) wave current was applied to the cathode of a Si chip during electroplating, and the PR (pulse-reverse) wave current was also applied for a comparison. The experimental results showed 100% filling rate into the TSV in one hour was achieved by the PPR electroplating process. At the interface between the Cu filling and Ti/ Au functional layers, no defect, such as a void, was found. Meanwhile, the electroplating by the PR current showed maximum 43% filling ratio into the TSV in an hour. The applied PPR wave form was confirmed to be effective to fill the TSV in a short time.

• 마이크로전자및패키징학회지
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• 제14권3호
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• pp.37-42
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• 2007

반도체 소자의 집적도가 높아짐에 따라 3D SiP에 대한 관심이 높아지고 전기도금법을 이용한 구리 via filling이 활발히 연구되어왔다. Via filling시 via 입구와 바닥에 전류밀도 차이로 인해 via 내부에 결함이 발생하기 쉽다. 여러 가지 유기물 첨가제와 전류인가 방식의 변화를 통한 via filling을 하였다. 첨가된 유기물은 PEG, SPS, JGB, PEI를 사용하였다. 유기물이 첨가된 용액을 이용하여 펄스와 역펄스 방법을 이용하여 via filling을 하였다. 유기물의 첨가에 따른 도금된 구리 입자의 크기 및 형상에 관하여 고찰하였으며 도금 후 via 시편의 단면을 FESEM으로 관찰하였다. JGB에 비하여 PEI를 사용한 경우 치밀한 도금층을 얻을 수 있었다. 2 step via filling을 사용한 경우 via filling 시간을 단축시킬 수 있었다.

• 대한금속재료학회지
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• 제50권2호
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• pp.152-158
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• 2012

The effect of current waveform on Cu filling into TSV (through-silicon via) and the bottom-up ratio of Cu were investigated for three dimensional (3D) Si chip stacking. The TSV was prepared on an Si wafer by DRIE (deep reactive ion etching); and its diameter and depth were 30 and $60{\mu}m$, respectively. $SiO_2$, Ti and Au layers were coated as functional layers on the via wall. The current waveform was varied like a pulse, PPR (periodic pulse reverse) and 3-step PPR. As experimental results, the bottom-up ratio by the pulsed current decreased with increasing current density, and showed a value of 0.38 on average. The bottom-up ratio by the PPR current showed a value of 1.4 at a current density of $-5.85mA/cm^2$, and a value of 0.91 on average. The bottom-up ratio by the 3-step PPR current increased from 1.73 to 5.88 with time. The Cu filling by the 3-step PPR demonstrated a typical bottom-up filling, and gave a sound filling in a short time.