• 제목/요약/키워드: propagation delay

검색결과 535건 처리시간 0.023초

화성암반에서 터널발파 진동측정치의 분석에 관한 사례 연구 (A Case Study on the Vibration Characteristics of Tunnel Blasting in Igneous Rock)

  • 윤성현;안명석;이광열
    • 화약ㆍ발파
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    • 제21권1호
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    • pp.69-76
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    • 2003
  • 터널 발파에 있어서 진동특성을 규명하기 위하여 V-cut 심발패턴으로 시험발파를 수행하고, '터널 진행방향'과 '터널 진행직각방향'의 두 방향에서 발파진동을 계측하였다. 최대지발당 장약량을 기준으로 지반의 진동 전달특성을 확인하기 위하여 자승근 환산거리와 삼승근 환산거리로 회귀분석을 수행한 결과 허용진동속도 3mm/sec에서 교차점은 62m였으며, 5mm/sec에서 교차점은 46m였다. 또한 터널 진행방향에서 측정한 경우가 터널 진행직각 방향에서 측정한 경우보다 진동수준은 크게 나타났으며, 삼승근 환산거리 적용시 감쇠특성이 더욱 우세하였다.

전류모드 CMOS 다치 논리회로를 이용한 32${\times}$32-Bit Modified Booth 곱셈기 설계 (Design of a 323${\times}$2-Bit Modified Booth Multiplier Using Current-Mode CMOS Multiple-Valued Logic Circuits)

  • 이은실;김정범
    • 대한전자공학회논문지SD
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    • 제40권12호
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    • pp.72-79
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    • 2003
  • 본 논문에서는 CMOS 다치 논리회로를 이용한 32×32 Modified Booth 곱셈기를 제시하였다. 이 곱셈기는 Radix-4 알고리즘을 이용하였으며, 전류모드 CMOS 4차 논리회로로 구현하였다. 설계한 곱셈기는 트랜지스터 수를 기존의 전압 모드 2진 논리 곱셈기에 비해 63.2%, 이전의 다치 논리 곱셈기에 비해 37.3% 감소시켰다. 이 곱셈기는 내부 구조를 규칙적으로 배열하여 확장성을 갖도록 하였다. 설계한 회로는 3.3V의 공급전압과 단위전류 10㎂를 사용하여, 0.3㎛ CMOS 기술을 이용하여 구현하였으며 HSPICE를 사용하여 검증하였다. 시뮬레이션 결과, 설계한 곱셈기는 5.9㎱의 최대 전달지연시간과 16.9mW의 평균 전력소모 특성을 갖는다.

유압관로에서 비정상유동의 압력전파특성 (Propagation Characteristics of Pressure Pulse of Unsteady Flow in n Hydraulic Pipeline)

  • 유영태;나기대;김지환
    • 대한기계학회논문집B
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    • 제26권1호
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    • pp.1-11
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    • 2002
  • Flow of fluid has been studied in various fields of fluid engineering. To hydraulic engineers, the unsteady flow such as pulsation and liquid hammering in pipes has been considered as a serious trouble. So we are supposed to approach the formalized mathematical model by using more exact momentum equation for fluid transmission lines. Most of recent studies fur pipe line have been studied without considerations of variation of viscosity and temperature, which are the main factors of pressure loss causing the friction of fluid inside pipe line. Frequency response experiments are carried out with use of a rotary sinusoidal flow generator to investigate wave equation take into account viscosity and temperature. But we observed that measured value of gains are reduced as temperature increased. And it was respectively observed that the measured value of gains are reduced and line width of gain is broadened out, when temperature was high in the same condition. As we confessed, pressure loss and phase delay are closely related with the length, diameter and temperature of pipe line. In addition, they are the most important factors, when we decide the momentum energy of working fluid.

RCM을 이용한 디젤 분무거동 및 자발화 특성에 관한 연구 (An Experimental Study on Diesel Spray Dynamics and Auto-Ignition Characteristics in the Rapid Compression Machine)

  • 강필중;김형모;김용모;김세원
    • 대한기계학회:학술대회논문집
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    • 대한기계학회 2000년도 춘계학술대회논문집B
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    • pp.447-452
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    • 2000
  • The low-emission and high-performance diesel combustion is an important issue in the combustion research community. In order to understand the detailed diesel flame field involving the complex Physical Processes, It Is quite desirable to study diesel spray dynamics, auto-ignition and spray flame propagation. Dynamics of fuel spray is a crucial element for air-fuel mixture formation flame stabilization and pollutant formation. In the present study, the diesel RCM (Rapid Compression Machine) and the Electric Control injection system have been designed and developed to investigate the effects of injection Pressure, injection timing, and intake air temperature on spray dynamics and diesel combustion processes. In terms of the macroscopic spray combustion characteristics it is observed that the fuel jet atomization and the droplet breakup processes become much faster by increasing the injection pressure and the spray angle. With increasing the cylinder pressure there is a tendency that the shape of spray pattern in the downstream region tends to be spherical due to the increase of air density and the corresponding drag force. Effects of intake temperature and injection pressure on auto-ignition is experimently analysed and discussed in detail.

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실시간 편광부호화에 의한 광병렬 가산기 구현 (Implementation of Optical Paralle Adder using Polarization Coding)

  • 조웅호;배장근;노덕수;김수중
    • 한국통신학회논문지
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    • 제17권12호
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    • pp.1484-1493
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    • 1992
  • 본 논문에서는 필터와 LCTV를 사용하여 광논리 게이트의 편광부호화를 제안하고, 올림수 지연시간을 개선하는 광병렬 가산기의 실시간 시스템을 제시한다. 셀의 편광부호화를 위하여 편광필터를 제작하고, 광병렬가산기 시스템에 필요한 광플립플롭 대신에 사용할 전기적인 시스템을 제작했다. 또, 광병렬가산기 시스템에 디코딩마스트 역할과 상호연결 역할을 동시에 할 수 있도록 광섬유를 사용했다. 실험결과에 의해 셀의 편광 부호화는 16가지 광논리함수를 표현할 수 있고, 광병렬 가산기는 실시간에 동작할 수 있음을 보였다.

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적응모델을 이용한 단일채널 능동 소음제어 (Single Channel Active Noise Control using Adaptive Model)

  • 김영달;이민명;정창경
    • 대한전기학회논문지:시스템및제어부문D
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    • 제49권8호
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    • pp.442-450
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    • 2000
  • Active noise control is an approach to noise reduction in which a secondary noise source that destructively interferes with the unwanted noise. In general, active noise control systems rely on multiple sensors to measure the unwanted noise field and the effect of the cancellation. This paper develops an approach that utilizes a single sensor. The noise field is modeled as a stochastic process, and a time-adaptive algorithm is used to adaptively estimate the parameters of the process. Based on these parameter estimates, a canceling signal is generated. Opppenheim model assumed that transfer function characteristics from the canceling source to the error sensor is only propagation delay. But this paper proposes a modified Oppenheim model by considering transfer characteristics of acoustic device and noise path. This transfer characteristics is adaptively cancelled by adaptive model. This is proved by computer simulation with artifically generated random noise and sine wave noise. The details of the proposed architecture, and theoretical simulation and experimental results of the noise cancellation system for three dimension enclosure are presented in the paper.

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회로 분할 유전자 알고리즘의 설계와 구현 (Design and Implementation of a Genetic Algorithm for Circuit Partitioning)

  • 송호정;송기용
    • 융합신호처리학회논문지
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    • 제2권4호
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    • pp.97-102
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    • 2001
  • CAD(Computer-Aided Design)에서의 분할(partitioning)은 기능의 최적화를 위해 대상의 그룹화(grouping)로 레이아웃(layout)에 면적과 전파지연 최소화를 위해 함께 위치할 소자를 결정하는 문제 또는 스케쥴링이나 유닛 선택을 위한 HLS(high level synthesis)에서의 변수나 연산에 대한 집단화 (clustering) 문제들을 포함하여 분할 문제에서 해를 얻기 위해 Kernighan-Lin 알고리즘 Fiduccia Mattheyses heuristic, 시뮬레이티드 어닐링(simulated annealing)등의 방식이 이용된다. 본 논문에서는 회로 분할 문제에 대하여 유전 알고리즘(GA; genetic algorithm)을 이용한 해 공간 탐색(soultion space search)방식을 제안하였으며, 제안한 방식을 시뮬레이티드 어닐링 방식과 비교, 분석하였다.

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Fault-tolerance Performance Evaluation of Fieldbus for NPCS Network of KNGR

  • Jung, Hyun-Gi;Seong, Poong-Hyun
    • Nuclear Engineering and Technology
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    • 제33권1호
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    • pp.1-11
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    • 2001
  • In contrast with conventional fieldbus researches which are focused merely on real-time performance, this study aims to evaluate the real-time performance of the communication system including fault-tolerant mechanisms Maintaining performance in presence of recoverable faults is very important in case that the communication network is applied to a highly reliable system such as next generation Nuclear. Power. Plant (NPP). If the tie characteristics meet the requirements of the system, the faults will be recovered by fieldbus recovery mechanisms and the system will be safe. If the time characteristics can not meet the requirements, the faults in the fieldbus can propagate to the system failure. In this study, for the purpose of investigating the time characteristics of fieldbus, the recoverable faults are classified and then the formulas that represent delays including recovery mechanisms are developed. In order to validate the proposed approach, we have developed a simulation model that represents the Korea Next Generation Reactor (KNGR) NSSS Process Control System (NPCS). The results of the simulation show us the reasonable delay characteristics of the fault cases with recovery mechanisms. Using the simulation results and the system requirements, we also can calculate the failure propagation probability from fieldbus to outer system.

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IoT 애플리케이션을 위한 AES 기반 보안 칩 설계 (A Design of an AES-based Security Chip for IoT Applications using Verilog HDL)

  • 박현근;이광재
    • 전기학회논문지P
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    • 제67권1호
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    • pp.9-14
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    • 2018
  • In this paper, we introduce an AES-based security chip for the embedded system of Internet of Things(IoT). We used Verilog HDL to implement the AES algorithm in FPGA. The designed AES module creates 128-bit cipher by encrypting 128-bit plain text and vice versa. RTL simulations are performed to verify the AES function and the theory is compared to the results. An FPGA emulation was also performed with 40 types of test sequences using two Altera DE0-Nano-SoC boards. To evaluate the performance of security algorithms, we compared them with AES implemented by software. The processing cycle per data unit of hardware implementation is 3.9 to 7.7 times faster than software implementation. However, there is a possibility that the processing speed grow slower due to the feature of the hardware design. This can be solved by using a pipelined scheme that divides the propagation delay time or by using an ASIC design method. In addition to the AES algorithm designed in this paper, various algorithms such as IPSec can be implemented in hardware. If hardware IP design is set in advance, future IoT applications will be able to improve security strength without time difficulties.

FPGA 기반의 냉연강판 핀홀 검출 시스템 (FPGA based System for Pinhole Detection in Cold Rolled Steel)

  • 하성길;이정은;문우성;백광렬
    • 제어로봇시스템학회논문지
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    • 제21권8호
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    • pp.742-747
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    • 2015
  • The quality of steel plate products is determined by the number of defects and the process problems are estimated by shapes of defects. Therefore pinholes defects of cold rolled steel have to be controlled. In order to improve productivity and quality of products, within each production process, the product is inspected by an adequate inspection system individually in the lines of steelworks. Among a number of inspection systems, we focus on the pinholes detection system. In this paper, we propose an embedded system using FPGA which can detect pinholes defects. The proposed system is smaller and more flexible than a traditional system based on expensive frame grabbers and PC. In order to detect consecutive defects, FPGAs acquire two dimensional image and process the image in real time by using correlation of lines. The proposed pinholes detection algorithm decreases arithmetic operations of image processing and also we designed the hardware to shorten the data path between logics due to decreasing propagation delay. The experimental results show that the proposed embedded system detects the reliable number of pinholes in real time.