• Journal of KIISE:Software and Applications
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• v.37 no.11
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• pp.851-858
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• 2010

Most mobile devices use a NAND flash memory as their secondary memory. A compressed code of the firmware is stored in the NAND flash memory of mobile devices in order to reduce the size and the loading time of the firmware from the NAND flash memory to a main memory. In order to use a demand paging properly, a compressed code should be decompressed very quickly. The thesis introduces a new dictionary based compression algorithm for the fast decompression. The introduced compression algorithm uses a different method with the current LZ method by storing the "exclusive or" value of the two instructions when the instruction for compression is not equal to the referenced instruction. Therefore, the thesis introduces a new compression format that minimizes the bit operation in order to improve the speed of decompression. The experimental results show that the decoding time is reduced up to 5 times and the compression ratio is improved up to 4% compared to the zlib. Moreover, the proposed compression method with the fast decoding time leads to 10-20% speed up of booting time compared to the booting time of the uncompressed method.

• IEMEK Journal of Embedded Systems and Applications
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• v.14 no.2
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• pp.103-111
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• 2019

The IoT-driven large-scaled systems consist of connected things with on-chip executable embedded software. These light-weighted embedded things have limited hardware space, especially small size of on-chip flash memory. In addition, on-chip embedded software in flash memory is not easy to update in runtime to equip with latest services in IoT-driven applications. It is becoming important to develop light-weighted IoT devices with various software in the limited on-chip flash memory. The remote instruction execution in cloud via IoT connectivity enables to provide high performance software execution with unlimited software instruction in cloud and low-power streaming of instruction execution in IoT edge devices. In this paper, we propose a Cloud-IoT asymmetric structure for providing high performance instruction execution in cloud, still low power code executable thing in light-weighted IoT edge environment using remote instruction execution. We propose a simulated approach to determine efficient partitioning of software runtime in cloud and IoT edge. We evaluated the instruction cloudification using remote instruction by determining the execution time by the proposed structure. The cloud-connected instruction set simulator is newly introduced to emulate the behavior of the processor. Experimental results of the cloud-IoT connected software execution using remote instruction showed the feasibility of cloudification of on-chip code flash memory. The simulation environment for cloud-connected code execution successfully emulates architectural operations of on-chip flash memory in cloud so that the various software services in IoT can be accelerated and performed in low-power by cloudification of remote instruction execution. The execution time of the program is reduced by 50% and the memory space is reduced by 24% when the cloud-connected code execution is used.

• Journal of the Korea Society for Simulation
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• v.18 no.3
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• pp.1-11
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• 2009

This paper illustrates a case study of PLC logic simulation in a car manufacturing system. It was developed to simulate and verify PLC control program for automobile panel AS/RS. Because car models become varied, the complexity of supply problem is increasing in the car manufacturing system. To cope with this problem, companies use the AS (automated storage) and RS (retrieval system) but it has logical complexity. Industrial automated process uses PLC code to control the AS/RS, however control information and control codes (PLC code) are difficult to understand. This paper suggests a PLC simulation environment, using 3D models and PLC code with realistic data. Data used in this simulation is based on realistic 3D model and I/O model, using actual size and PLC signals, respectively. The environment is similar to a real factory; users can verify and test the PLC code using this simulation before the implementation of AS/RS. Proposed simulation environment can be used for test run of AS/RS to reduce implementation time and cost.

• Journal of Software Assessment and Valuation
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• v.15 no.1
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• pp.55-62
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• 2019

The needs for small size and low power consumption of information devices is being implemented with SOC technology that implements the program on a single chip in Internet of Thing. Copyright disputes due to piracy are increasing in semiconductor chips as well, arising from disputes in the chip implementation of the design house and chip implementation by the illegal use of the source code. However, since the final chip implementation is made in the design house, it is difficult to protect the copyright. In this paper, we deal with the analysis method for extracting similarity and the criteria for setting similarity judgment in the dispute of source code written in HDL language. Especially, the chip which is manufactured based on the same specification will be divided into the same configuration and the code type.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.12
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• pp.1-12
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• 1998

In this paper, a design and implementation of VHDL-to-C mapping in the VHDL compiler back-end is described. The analyzed data in an intermediate format(IF), produced by the compiler front-end, is transformed into a C-code model of VHDL semantics by the VHDL-to-C mapper. The C-code model for VHDL semantics is based on a functional template, including declaration, elaboration, initialization and execution parts. The mapping is carried out by utilizing C mapping templates of 129 types classified by mapping units and functional semantics, and iterative algorithms, which are combined with terminal information, to produce C codes. In order to generate the C program, the C codes are output to the functional template either directly or by combining the higher mapping result with intermediate mapping codes in the data queue. In experiments, it is shown that the VHDL-to-C mapper could completely deal with the VHDL analyzed programs from the compiler front-end, which deal with about 96% of major VHDL syntactic programs in the Validation Suite. As for the performance, it is found that the code size of VHDL-to-C is less than that of interpreter and worse than direct code compiler of which generated code is increased more rapidly with the size of VHDL design, and that the VHDL-to-C timing overhead is needed to be improved by the optimized implementation of mapping mechanism.

• The KIPS Transactions:PartA
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• v.13A no.4 s.101
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• pp.275-288
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• 2006

Rapid design space exploration is crucial to customizing embedded system design for exploiting the application behavior. As the time-to-market becomes a key concern of the design, the approach based on an application specific instruction-set processor (ASIP) is considered more seriously as one alternative design methodology. In this approach, the instruction set architecture (ISA) for a target processor is frequently modified to best fit the application with regard to code size and speed. Two goals of this paper is to introduce our new retargetable compiler and how it has been used in ASIP-based design space exploration for a popular digital signal processing (DSP) application. Newly developed retargetable compiler provides not only the functionality of previous retargetable compilers but also visualizes the features of the application program and profiles it so that it can help architecture designers and application programmers to insert new application specific instructions into target architecture for performance increase. Given an initial RISC-style ISA for the target processor, we characterized the application code and incrementally updated the ISA with more application specific instructions to give the compiler a better chance to optimize assembly code for the application. We get 32% performance increase and 20% program size reduction using 6 audio codec specific instructions from retargetable compiler. Our experimental results manifest a glimpse of evidence that a higgly retargetable compiler is essential to rapidly prototype a new ASIP for a specific application.

• Proceedings of the Korea Society for Industrial Systems Conference
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• 2002.06a
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• pp.170-176
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• 2002

Java language is a representative object-oriented language that is used at the various platform and fields. A structure of java language is simpler than traditional procedural-oriented language because of characters of object-oriented language But it is difficult to debug complicated java programs. Debugging has always been a costly part of software development. Syntax errors of java programs is easily found by the current debugging system. But it is difficult to locate logical errors included in java programs. Traditional debugging techniques locating logical errors in java program have been still used with conventional methods that are used at procedural-oriented languages. Unfortunately, these traditional methods are often inadequate for the task of isolating specific program errors. Debugger users may spend considerable time debugging code of program development with sequential methods according as program size is large and is complicated. It is important to easily locate errors included in java program in the software development. In this paper, we apply algorithmic debugging method that debugger user can easily debug programs to java program. This method executes a program and makes an execution tree from calling relation of functions. And it locates errors at the execution tree. So, Algorithmic debugging method can reduce the number of debugging than conventional sequential method.

• Journal of the Korea Society of Computer and Information
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• v.19 no.2
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• pp.151-159
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• 2014

We discuss the implementation of a compiler for an imperative programming language, using monad in Haskell. This compiler involves a recursive-descent parser conducting nondeterministic parsing, in which backtracking occurs to try with other rules when the application of a production rule fails to parse an input string. Haskell has some strong facilities for parsing. Its algebraic types represent abstract syntax trees in a smooth way, and program codes by monad parsing are so concise that they are highly readable and code size is reduced significantly, comparing with other languages. We also deal with the runtime environment of the assembler and code generation whose target is the Stack-Assembly language based on a stack machine.

• Journal of Internet Computing and Services
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• v.21 no.5
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• pp.129-137
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• 2020

Recently, software size and program code complexity have increased due to application to various fields of software. Accordingly, the existence of program bugs inevitably occurs, and the cost of software maintenance is increasing. In open source projects, developers spend a lot of debugging time when solving a bug report assigned. To solve this problem, in this paper, we apply SeqGAN algorithm to software bug repair. In detail, the SeqGAN model is trained based on the source code. Open similar source codes during the learning process are also used. To evaluate the suitability for the generated candidate patch, a fitness function is applied, and if all test cases are passed, software bug correction is considered successful. To evaluate the efficiency of the proposed model, it was compared with the baseline, and the proposed model showed better repair.

• Journal of Digital Convergence
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• v.17 no.9
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• pp.185-192
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• 2019

The introduction of smart technology provides accuracy, safety, and efficiency to both physicians and patients. Although interest in a clear aligner is increasing among users worldwide, the current clear aligner requires a visit to the hospital every one or two weeks for replacement, which is a very cumbersome process. There is also confusion among dentists and patients because about 40 to 80 devices are made, and calibration is done based on the order and duration of the clear aligner. Therefore, this study designed and developed a clear aligner management system so that communication between the patient and dentist can be smoothly performed by inserting the QR code into the transparent correction device. As a result, the size of the QR code was recognized as $6{\ast}6mm^2$ which can be used in the oral and the recognition distance was 100% within 12 cm. Since the dentist can remotely manage the patient with the proposed system and improve the correction effect, it is possible to manage patients abroad, as well as domestically.