• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2009.01a
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• pp.258-262
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• 2009

In this paper, we propose an effective memory reduction algorithm to reduce the amount of reference frame buffer and memory bandwidth in video encoder and decoder. In general video codecs, decoded previous frames should be stored and referred to reduce temporal redundancy. Recently, reference frames are recompressed for memory efficiency and bandwidth reduction between a main processor and external memory. However, these algorithms could hurt coding efficiency. Several algorithms have been proposed to reduce the amount of reference memory with minimum quality degradation. They still suffer from quality degradation with fixed-bit allocation. In this paper, we propose an adaptive block-based min-max quantization that considers local characteristics of image. In the proposed algorithm, basic process unit is $8{\times}8$ for memory alignment and apply an adaptive quantization to each $4{\times}4$ block for minimizing quality degradation. We found that the proposed algorithm could improve approximately 37.5% in coding efficiency, compared with an existing memory reduction algorithm, at the same memory reduction rate.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.5_6
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• pp.347-352
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• 2004

This thesis deals with a task scheduling on a message-passing system. Scheduling and allocation are very important issues since the inappropriate scheduling of tasks cannot exploit the true potential of the system and it can offset the grain from parallelization. It is difficult to apply previous schemes to message-passing system, because previous schemes assume the shared memory system. This thesis proposes an modified priority function and processor selection technique that consider the problems caused by the difference between previous models and message-passing environments. The priority function includes the cumulative communication cost which causes task execution to be delayed. The processor selection technique avoids the situation that a child task is assigned to the same Processor allocated to its parent task that has other unscheduled child tasks. We showed by some simulations that our modified features of task scheduling algorithm can make the better scheduling results than the previous algorithms.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.41 no.2
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• pp.9-22
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• 2004

This paper presents a parallel genetic algorithm for the Multi-disk data allocation problem an NP-complete problem. This problem is to find a method to distribute a Binary Cartesian Product File on disk-arrays to maximize parallel disk I/O accesses. A Sequential Genetic Algorithm(SGA), DAGA, has been proposed and showed the superiority to the other proposed methods, but it has been observed that DAGA consumes considerably lengthy simulation time. In this paper, a parallel version of DAGA(ParaDAGA) is proposed. The ParaDAGA is a 2-dimension torus-based Parallel Genetic Algorithm(PGA) and it is based on a distributed population structure. The ParaDAGA has been implemented on the parallel computer simulated on a single processor platform. Through the simulation, we study the impact of varying ParaDAGA parameters and compare the quality of solution derived by ParaDAGA and DAGA. Comparing the quality of solutions, ParaDAGA is superior to DAGA in all cases of configurations in less simulation time.

• Journal of KIISE:Databases
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• v.28 no.4
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• pp.732-741
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• 2001

In the relational database systems the join operation is one of the most time-consuming query operations. Many parallel join algorithms have been developed 개 reduce the execution time Multiple hash join algorithm using allocation tree is one of the most efficient ones. However, it may have some delay on the processing each node of allocation tree, which is occurred in tuple-probing phase by the difference between one page reading time of outer relation and the processing time of already read one. This delay problem was solved by using the concept of synchronization of page execution time with we had proposed In this paper the effects of the performance improvements in each node of the allocation tree are extended to the whole allocation tree and the performance evaluation about that is processed. In addition we propose an efficient algorithm for multiple hash joins in limited number of processor environments according to the relationship between the number of input relations in the allocation tree and the number of processors allocated to the tree. Finally. we analyze the performance by building the analytical cost model and verify the validity of it by various performance comparison with previous method.

• Proceedings of the Korean Information Science Society Conference
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• 2002.04a
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• pp.589-591
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• 2002

본 논문에서는 메쉬 구조의 다중처리시스템을 위한 새로운 할당방법을 제안한다. 이 할당방법은 다른 가용 서브메쉬와 중첩되지 않는 독립 가용 서브메쉬를 유형에 따라 분류하여 유형별 가용 서브메쉬 리스트를 생성한다. 그리고 태스크의 유형에 따라 해당 유형별 가용 서브메쉬 리스트에서 최적할당이 가능한 서브메쉬를 찾음으로써 서브메쉬를 탐색하는데 소요되는 시간을 줄인다. 이 때 서브메쉬를 찾지 못하면 확장지수를 이용하여 더 큰 가용 서브메쉬를 형성한 후 할당함으로써 태스크의 대기 시간을 줄이고, 이 결과로 외적단편화를 줄이는 효과도 얻는다. 또한 할당 해제시 독립 가용 서브메쉬는 다른 가용 서브메쉬의 크기 에 변화를 주지 않기 때문에 그 유형에 따라 유형별 가용 서브메쉬 리스트에 삽입한다. 그럼으로써 할당 해제 후 유형별 가용 서브메쉬 리스트를 재생성하기 위해 전체 메쉬 구조를 탐색 할 필요가 없어진다.

• The KIPS Transactions:PartA
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• v.10A no.1
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• pp.43-48
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• 2003

Two-dimensional packing algorithm can be used for allocating submeshes in mesh multiprocessor systems. Previously, we developed an efficient packing algorithm called TP heuristic, and showed how the results of the packing could be used for allocating submeshes. In this paper, we present theoretical performance bounds for TP heuristic. We also present a parallel version of the algorithm that consumes reduced time when it is executed by multiple processors in mesh multiprocessors.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.412-415
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• 1999

In this paper, we describe an implementation of the B-Link bus interface logic for a directory controller and a remote access cash controller in the SCI-based CC-NUMA multimedia server developed by ETRI . The CC-NUMA multimedia server is composed of a number of Pentium III SHV nodes and a SCI interconnection network. To communicate with remote nodes, each node has a CC-Agent which consists of a processor bus interface(PIF). a directory controller(DC), a remote access cash controller(RC), and two SCI 1ink controllers(LCs). The B-Link bus interface logic is developed for a directory controller and a remote access cash controller in order to communicate with a SCI link controller on a B-Link bus. It consists of a sending master controller a receiving slave controller, and asynchronous data buffers. And It performs a self-arbitration, a data packet transmission, a queue allocation, an early terminal ion. and a cut-through data path.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.3
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• pp.89-99
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• 1995

One of the hardest problems that limit real application of production system is its slowness. One way to overcome this problem is to speed up the matching operation which occupies more than 90% of the total execution time. In this paper, we try to speed up the matching operation with parallel execution of a typical pattern matching algorithm, RETE, in a multiprocessor environment, This requires not only to make partitions of the rules but also to allocate the partitioned rules to processors, respectively. A partition strategy is proposed to make groups of similar rules by evaluating the similarity of rules according to the number of common conditions between rules. An allocation strategy is proposed to make the load of each processor even by assigning the different priority to the group of rules according to the expected amount of time required for matching operation. To compare with the existing methods, we perform simulation using OPS5 sample programs. The simulation results show that the proposed methods can improve the performance of production system.

• Proceedings of the Korean Information Science Society Conference
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• 2003.04a
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• pp.148-150
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• 2003

본 논문에서는 인터넷 종단 호스트에서 공유 자원의 대역폭 제약조건과 종료시한 제악조건 모두를 만족시킬 수 있는 자원 할당 구조를 제안한다. 제안된 구조는 두 단계로 구성된다. 상위 단계에서는 비례 분배 스케줄러(proportional share scheduler)인 EFT-C/D (Earliest Finish Time Credit/Debit) 스케줄러가 수행된다. 이 스케줄러는 CPU와 같은 시분할 공유 자원을 하위 단계 스케줄러들에게 지정된 비율로 분배하는 역할을 한다. 그리고 하위 단계에서는 서로 다른 시간 제약조건이 부여된 태스크들을 스케줄링 하기위해 다양한 실시간 스케줄러가 수행된다. 본 연구의 주요 성과는 두 가지로 요약된다. 첫째, 이상적인 GPS (Generalized Processor Sharing) 서버와 거의 동등한 수준으로 자원을 공평하게 분배하는 EFT-C/D 알고리즘을 개발하였다. 둘째, 하위 단계에서 수행되는 EDF 스케줄러에 대해 이용율(utilization)에 기반한 스케룰링 가능성 분석 방법을 개발하였다. 이 방법은 주어진 태스크 집합에 대해 단순히 이용율만을 계산하여 스케줄링 가능성을 판별할 수 있다. 따라서 새로운 태스크가 생성될 때 수락 여부를 시스템 수행 중에 제어할 수 있는 장점이 있다.

• Annual Conference of KIPS
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• 2003.05a
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• pp.125-128
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• 2003

본 논문에서는 메쉬 구조 다중컴퓨터 시스템을 위한 새로운 서브메쉬 할당방법을 제안한다. 이 할당방법의 특징을 외적단편화로 인한 할당지연을 최소화하여 태스크 대기시간을 단축하는 것이다. 2차원 메쉬 구조에서는 할당 서브메쉬에 의해 상하, 좌우로 양분되는 프로세서 단편들을 연결하여 더 큰 가용 서브메쉬를 형성할 수 없는 구조적인 한계 때문에 외적단편화로 인한 서브메쉬의 할당지연이 발생한다. 이러한 할당지연은 태스크의 대기시간을 증가시키기 때문에 시스템의 성능을 저하시킨다. 따라서 본 논문에서는 외적단편화로 인해 서브메쉬의 할당지연이 발생하면 할당서브메쉬에서 수행중인 태스크들을 다른 가용 서브메쉬에 재배치하고 프로세서 단편들을 통합하여 할당함으로써 태스크의 대기시간을 줄인다. 시뮬레이션을 통하여 제안한 할당방법이 태스크의 대기시간을 줄이는 면에서 기존의 할당방법들 보다 우수함을 보인다.